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244 lines
7.7 KiB
244 lines
7.7 KiB
from cocotb.triggers import Combine
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from pyuvm import (
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uvm_test,
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uvm_sequence,
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uvm_sequence_item,
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uvm_sequencer,
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uvm_driver,
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uvm_component,
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uvm_subscriber,
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uvm_env,
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uvm_factory,
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uvm_analysis_port,
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uvm_tlm_analysis_fifo,
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uvm_get_port,
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ConfigDB,
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UVMConfigItemNotFound,
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)
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from vsc import get_coverage_report
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from VaiBfm import VaiBfm, Mode
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from Coverage import constraints, covergroup
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from Crypto.Cipher import AES
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import cocotb
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import pyuvm
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import vsc
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@pyuvm.test()
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class AesTest(uvm_test):
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def build_phase(self):
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self.env = AesEnv("env", self)
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def end_of_elaboration_phase(self):
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self.test_all = TestAllSeq.create("test_all")
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async def run_phase(self):
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self.raise_objection()
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await self.test_all.start()
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self.drop_objection()
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@pyuvm.test()
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class ParallelTest(AesTest):
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def end_of_elaboration_phase(self):
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uvm_factory().set_type_override_by_type(TestAllSeq, TestAllParallelSeq)
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return super().end_of_elaboration_phase()
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# Virtual sequence that starts other sequences
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class TestAllSeq(uvm_sequence):
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async def body(self):
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# get the sequencer handle
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seqr = ConfigDB().get(None, "", "SEQR")
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enc_rand_seq = EncRandSeq("enc_random")
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dec_rand_seq = DecRandSeq("dec_random")
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await enc_rand_seq.start(seqr)
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await dec_rand_seq.start(seqr)
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# Running encryption and decryption sequences in parallel
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class TestAllParallelSeq(uvm_sequence):
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async def body(self):
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seqr = ConfigDB().get(None, "", "SEQR")
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enc_rand_seq = EncRandSeq("enc_random")
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dec_rand_seq = DecRandSeq("dec_random")
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enc_rand_task = cocotb.start_soon(enc_rand_seq.start(seqr))
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dec_rand_task = cocotb.start_soon(dec_rand_seq.start(seqr))
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await Combine(enc_rand_task, dec_rand_task)
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# Sequence item which holds the stimuli for one operation
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class AesSeqItem(uvm_sequence_item):
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def __init__(self, name, mode, key, data):
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super().__init__(name)
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self.mode = mode
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self.key = key
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self.data = data
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def __eq__(self, other):
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same = (
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self.mode == other.mode
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and self.key == other.key
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and self.data == other.data
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)
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return same
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def __str__(self):
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return f"{self.get_name()} : Mode: 0b{self.mode:01x} \
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Key: 0x{self.key:016x} Data: 0x{self.data:016x}"
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# Abstract basis sequence class
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# set_operands() has to be implemented by class that inherits from this class
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class BaseSeq(uvm_sequence):
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async def body(self):
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self.cr = constraints()
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for _ in range(20):
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aes_tr = AesSeqItem("aes_tr", 0, 0, 0)
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await self.start_item(aes_tr)
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self.set_operands(aes_tr)
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await self.finish_item(aes_tr)
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def set_operands(self, tr):
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pass
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# Sequence for encryption tests with random stimuli
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class EncRandSeq(BaseSeq):
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def set_operands(self, tr):
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self.cr.randomize()
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tr.mode = 0
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tr.key = self.cr.key
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tr.data = self.cr.data
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# Sequence for decryption tests with random stimuli
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class DecRandSeq(BaseSeq):
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def set_operands(self, tr):
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self.cr.randomize()
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tr.mode = 1
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tr.key = self.cr.key
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tr.data = self.cr.data
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class Driver(uvm_driver):
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def build_phase(self):
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self.ap = uvm_analysis_port("ap", self)
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def start_of_simulation_phase(self):
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self.bfm = VaiBfm()
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async def launch_tb(self):
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await self.bfm.reset()
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self.bfm.start_tasks()
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async def run_phase(self):
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await self.launch_tb()
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while True:
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op = await self.seq_item_port.get_next_item()
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await self.bfm.send_op(op.mode, op.key, op.data)
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result = await self.bfm.get_output()
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self.ap.write(result)
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self.seq_item_port.item_done()
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class Scoreboard(uvm_component):
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def build_phase(self):
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self.input_fifo = uvm_tlm_analysis_fifo("input_fifo", self)
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self.output_fifo = uvm_tlm_analysis_fifo("output_fifo", self)
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self.input_get_port = uvm_get_port("input_get_port", self)
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self.output_get_port = uvm_get_port("output_get_port", self)
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self.input_export = self.input_fifo.analysis_export
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self.output_export = self.output_fifo.analysis_export
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self.passed = True
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def connect_phase(self):
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self.input_get_port.connect(self.input_fifo.get_export)
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self.output_get_port.connect(self.output_fifo.get_export)
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def check_phase(self):
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while self.output_get_port.can_get():
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_, result = self.output_get_port.try_get()
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op_success, op = self.input_get_port.try_get()
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if not op_success:
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self.logger.critical(f"result {result} had no input operation")
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else:
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(mode, key, data) = op
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aes = AES.new(key.buff, AES.MODE_ECB)
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if not mode:
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reference = aes.encrypt(data.buff)
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else:
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reference = aes.decrypt(data.buff)
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if result.buff == reference:
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self.logger.info(
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f"PASSED: {Mode(mode).name} 0x{data.integer:032x} with key "
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f"0x{key.integer:032x} = 0x{result.integer:032x}"
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)
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else:
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self.logger.error(
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f"FAILED: {Mode(mode).name} 0x{data.integer:032x} with key "
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f"0x{key.integer:032x} = 0x{result.integer:032x}, "
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f"expected 0x{int.from_bytes(reference, 'big'):032x}"
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)
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self.passed = False
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def report_phase(self):
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assert self.passed, "Test failed"
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class Monitor(uvm_component):
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def __init__(self, name, parent, method_name):
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super().__init__(name, parent)
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self.bfm = VaiBfm()
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self.get_method = getattr(self.bfm, method_name)
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def build_phase(self):
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self.ap = uvm_analysis_port("ap", self)
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async def run_phase(self):
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while True:
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datum = await self.get_method()
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self.logger.debug(f"MONITORED {datum}")
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self.ap.write(datum)
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# Coverage collector and checker
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class Coverage(uvm_subscriber):
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def start_of_simulation_phase(self):
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self.cg = covergroup()
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try:
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self.disable_errors = ConfigDB().get(self, "", "DISABLE_COVERAGE_ERRORS")
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except UVMConfigItemNotFound:
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self.disable_errors = False
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def write(self, data):
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(mode, key, _) = data
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self.cg.sample(mode, key)
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def report_phase(self):
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if not self.disable_errors:
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if self.cg.get_coverage() != 100.0:
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self.logger.warning("Functional coverage incomplete.")
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else:
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self.logger.info("Covered all operations")
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with open("results/tb_aes_fcover.txt", "a", encoding="utf-8") as f:
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f.write(get_coverage_report(details=True))
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vsc.write_coverage_db("results/tb_aes_fcover.xml")
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# AES test bench environment
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# Creates instances of components and connects them
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class AesEnv(uvm_env):
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def build_phase(self):
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self.seqr = uvm_sequencer("seqr", self)
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ConfigDB().set(None, "*", "SEQR", self.seqr)
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self.driver = Driver.create("driver", self)
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self.input_mon = Monitor("input_mon", self, "get_input")
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self.coverage = Coverage("coverage", self)
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self.scoreboard = Scoreboard("scoreboard", self)
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def connect_phase(self):
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self.driver.seq_item_port.connect(self.seqr.seq_item_export)
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self.input_mon.ap.connect(self.scoreboard.input_export)
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self.input_mon.ap.connect(self.coverage.analysis_export)
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self.driver.ap.connect(self.scoreboard.output_export)
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