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42 lines
964 B
42 lines
964 B
# Default test
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DUT ?= uarttx
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ifeq (${DUT}, wishbone)
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TOPLEVEL := wishboneslavee
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SIM_ARGS := -gSimulation=true \
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-gAddressWidth=8 \
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-gDataWidth=16
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else
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TOPLEVEL := ${DUT}
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endif
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# Simulator (GHDL) & RTL related
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SIM := ghdl
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TOPLEVEL_LANG := vhdl
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VHDL_SOURCES_libvhdl := ../libvhdl/common/UtilsP.vhd
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VHDL_SOURCES := ../libvhdl/syn/*.vhd \
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../cryptocores/aes/rtl/vhdl/*.vhd
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SIM_BUILD := work
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COMPILE_ARGS := --std=08
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SIM_ARGS += \
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--wave=results/${TOPLEVEL}.ghw \
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--psl-report=results/${TOPLEVEL}_psl.json \
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--vpi-trace=results/${TOPLEVEL}_vpi.log
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# Cocotb related
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MODULE := tb_${DUT}
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COCOTB_LOG_LEVEL := DEBUG
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CUSTOM_COMPILE_DEPS := results
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COCOTB_RESULTS_FILE := results/${TOPLEVEL}.xml
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include $(shell cocotb-config --makefiles)/Makefile.sim
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results:
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mkdir -p results
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.PHONY: clean
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clean::
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rm -rf *.o __pycache__ uarttx uartrx wishboneslavee aes results
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