tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Add example for dlatchsr error

6 years ago

.PHONY: dlatch
dlatch: dlatch.vhd dlatch_t.sv dlatch_f.sby
	sby -f -d work dlatch_f.sby

.PHONY: clean
clean:
	rm -rf work