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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/vai_fifo/symbiyosys.sby

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Add (non-functional yet) VAI-FIFO
3 years ago
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  1. [tasks]
  2. cover
  3. bmc
  4. prove
  5. 

  6. [options]
  7. depth 25
  8. cover: mode cover
  9. bmc: mode bmc
  10. prove: mode prove
  11. 

  12. [engines]
  13. cover: smtbmc z3
  14. bmc: smtbmc z3
  15. #abc bmc3
  16. prove: abc pdr
  17. 

  18. [script]
  19. ghdl --std=08 -gFormal=true -gDepth=16 -gWidth=16 fifo.vhd vai_fifo.vhd -e vai_fifo
  20. prep -top vai_fifo
  21. #chformal -assume -remove vai_fifo/*
  22. chformal -assume -remove vai_fifo/i_fifo
  23. 

  24. [files]
  25. ../fifo/fifo.vhd
  26. vai_fifo.vhd