tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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ci: add GitHub Actions workflow 'Test'

4 years ago

#!/usr/bin/env bash

_matrix=''
for item in $(cat tests.txt); do
  _matrix+="'$item', "
done

echo "::set-output name=matrix::[$_matrix]"