Trying to verify Verilog/VHDL designs with formal methods and tools
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  1. name: Test
  2. on:
  3. push:
  4. pull_request:
  5. jobs:
  6. Matrix:
  7. runs-on: ubuntu-latest
  8. name: '🧾 Generate Test matrix'
  9. outputs:
  10. matrix: ${{ steps.generate.outputs.matrix }}
  11. steps:
  12. - name: '🧰 Checkout'
  13. uses: actions/checkout@v2
  14. - id: generate
  15. name: '🧾 generate_matrix.sh'
  16. run: ./.github/generate_matrix.sh
  17. Test:
  18. needs: Matrix
  19. runs-on: ubuntu-20.04
  20. strategy:
  21. fail-fast: false
  22. matrix:
  23. design: ${{ fromJson(needs.Matrix.outputs.matrix) }}
  24. name: '🛳️ Test · ${{ matrix.design }}'
  25. steps:
  26. - name: '🧰 Checkout'
  27. uses: actions/checkout@v1
  28. with:
  29. submodules: recursive
  30. - name: '🛳️ Execute make ${{ matrix.design }} in hdlc/formal:all'
  31. uses: docker://hdlc/formal:all
  32. with:
  33. args: make ${{ matrix.design }}
  34. env:
  35. BUILD_NAME: ACCEPTANCE