tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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ci: add GitHub Actions workflow 'Test'

4 years ago

Add simple top levem Makefile & test list

4 years ago

DESIGNS := $(shell cat tests.txt)

.PHONY: ${DESIGNS} all clean

all: ${DESIGNS}

$(DESIGNS):
	make -C $@ all -j$(nproc)

clean:
	for dir in $(DESIGNS); do \
	  make -C $$dir clean;    \
	done