tmeissner
/
formal_hw_verification
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 6 Wiki Activity
Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
52 Commits
3 Branches
324 KiB
Tree: 2bc122eb5d
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '2bc122eb5d'
${ noResults }
formal_hw_verification/counter/symbiyosys.sby

22 lines
243 B
Raw Normal View History

Making counter design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module when using generics * Add some simple PSL assertions
5 years ago
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
​
 
  1. [tasks]
  2. cover
  3. bmc
  4. prove
  5. 

  6. [options]
  7. depth 25
  8. cover: mode cover
  9. bmc: mode bmc
  10. prove: mode prove
  11. 

  12. [engines]
  13. cover: smtbmc z3
  14. bmc: smtbmc z3
  15. prove: smtbmc z3
  16. 

  17. [script]
  18. ghdl --std=08 -fpsl counter.vhd -e counter
  19. prep -auto-top
  20. 

  21. [files]
  22. counter.vhd