tmeissner
/
formal_hw_verification
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 6 Wiki Activity
Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
28 Commits
3 Branches
324 KiB
Tree: 30ef117823
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '30ef117823'
${ noResults }
formal_hw_verification/.gitignore

1 line
9 B
Raw Normal View History

Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv
6 years ago
 
  1. */work/*