Trying to verify Verilog/VHDL designs with formal methods and tools
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  1. .PHONY: cover prove all clean
  2. all: cover bmc prove
  3. cover: vai_reg.vhd symbiyosys.sby
  4. sby --yosys "yosys -m ghdl" -f -d work/vai_reg-$@ symbiyosys.sby $@
  5. bmc: vai_reg.vhd symbiyosys.sby
  6. sby --yosys "yosys -m ghdl" -f -d work/vai_reg-$@ symbiyosys.sby $@
  7. prove: vai_reg.vhd symbiyosys.sby
  8. sby --yosys "yosys -m ghdl" -f -d work/vai_reg-$@ symbiyosys.sby $@
  9. clean:
  10. rm -rf work