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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/vai_reg/symbiyosys.sby

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Add make targets and SymbiYosys tasks for cover, bmc & prove
5 years ago
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Add simple VAI register file as base to try to formal verify FSM designs
6 years ago
Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module
5 years ago
Add make targets and SymbiYosys tasks for cover, bmc & prove
5 years ago
​
​
Add simple VAI register file as base to try to formal verify FSM designs
6 years ago
​
Add make targets and SymbiYosys tasks for cover, bmc & prove
5 years ago
​
​
Add simple VAI register file as base to try to formal verify FSM designs
6 years ago
​
Adapt to use GHDL as plugin for Yosys VHDL synthesis
5 years ago
Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module
5 years ago
Add simple VAI register file as base to try to formal verify FSM designs
6 years ago
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  1. [tasks]
  2. cover
  3. bmc
  4. prove
  5. 

  6. [options]
  7. depth 25
  8. cover: mode cover
  9. bmc: mode bmc
  10. prove: mode prove
  11. 

  12. [engines]
  13. cover: smtbmc z3
  14. bmc: abc bmc3
  15. prove: abc pdr
  16. 

  17. [script]
  18. ghdl --std=08 -fpsl vai_reg.vhd -e vai_reg
  19. prep -auto-top
  20. 

  21. [files]
  22. vai_reg.vhd