Trying to verify Verilog/VHDL designs with formal methods and tools
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43 lines
849 B

  1. [*]
  2. [*] GTKWave Analyzer v3.3.91 (w)1999-2018 BSI
  3. [*] Sat Dec 29 18:53:51 2018
  4. [*]
  5. [dumpfile_size] 13145
  6. [timestart] 0
  7. [size] 1344 495
  8. [pos] -1 -1
  9. *-5.329921 40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
  10. [treeopen] vai_reg.
  11. [sst_width] 193
  12. [signals_width] 199
  13. [sst_expanded] 1
  14. [sst_vpaned_height] 130
  15. @28
  16. vai_reg.properties.Clk_i
  17. @200
  18. -VAI req
  19. @28
  20. vai_reg.properties.DinStart_i
  21. vai_reg.properties.DinStop_i
  22. @22
  23. vai_reg.properties.Din_i[7:0]
  24. @28
  25. vai_reg.properties.DinValid_i
  26. vai_reg.properties.DinAccept_o
  27. @200
  28. -VAI ack
  29. @28
  30. vai_reg.properties.DoutStart_o
  31. vai_reg.properties.DoutStop_o
  32. @22
  33. vai_reg.properties.Dout_o[7:0]
  34. @28
  35. vai_reg.properties.DoutValid_o
  36. vai_reg.properties.DoutAccept_i
  37. @200
  38. -Internal
  39. @28
  40. vai_reg.properties.s_fsm_state[2:0]
  41. vai_reg.properties.s_register[63:0]
  42. [pattern_trace] 1
  43. [pattern_trace] 0