Trying to verify Verilog/VHDL designs with formal methods and tools
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  1. [options]
  2. mode prove
  3. depth 30
  4. wait on
  5. [engines]
  6. smtbmc
  7. abc pdr
  8. [script]
  9. verific -vhdl counter.vhd
  10. verific -formal counter_t.sv
  11. prep -top counter_t
  12. [files]
  13. counter.vhd
  14. counter_t.sv