tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Add counter as example for initial reset problems

6 years ago

Make the unbounded prove work * Fixed bug in check for end value in counter unit ;) * Use abc engine with pdr solver * Add asserts for reset

6 years ago

Add counter as example for initial reset problems

6 years ago

[options]
mode prove
multiclock on

[engines]
#smtbmc
abc pdr

[script]
verific -vhdl counter.vhd
verific -formal counter_t.sv
prep -top counter_t

[files]
counter.vhd
counter_t.sv