tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

5 lines

43 B

Raw Normal View History

ci: add GitHub Actions workflow 'Test'

4 years ago

Add fwft-fifo & use that for vai-fifo; minor fixes

4 years ago

ci: add GitHub Actions workflow 'Test'

4 years ago

alu
counter
fifo
fwft_fifo
vai_fifo
vai_reg