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Fix chformal selection parameter; add reset restrict to top-level

master
T. Meissner 4 years ago
parent
commit
4adea23c43
3 changed files with 10 additions and 6 deletions
  1. +1
    -1
      README.md
  2. +2
    -4
      vai_fifo/symbiyosys.sby
  3. +7
    -1
      vai_fifo/vai_fifo.vhd

+ 1
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README.md View File

@ -21,7 +21,7 @@ A simple counter design in VHDL. The testbench contains various simple propertie
A simple synchronous FIFO with various checks for write/read pointers, data and flags. A simple synchronous FIFO with various checks for write/read pointers, data and flags.
### vai_fifo ### vai_fifo
A simple FIFO with valid-accept interface. Consists of the fifo unit and some glue logic doing fifo<->vai interface conversion.
A simple FIFO with valid-accept-interface. Consists of fifo as sub-unit and some glue logic doing fifo<->vai interface conversion. This design serves as an example how to verify designs with sub-units containing formal checks.
### vai_reg ### vai_reg
A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs. A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs.

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vai_fifo/symbiyosys.sby View File

@ -11,15 +11,13 @@ prove: mode prove
[engines] [engines]
cover: smtbmc z3 cover: smtbmc z3
bmc: smtbmc z3
#abc bmc3
bmc: abc bmc3
prove: abc pdr prove: abc pdr
[script] [script]
ghdl --std=08 -gFormal=true -gDepth=16 -gWidth=16 fifo.vhd vai_fifo.vhd -e vai_fifo ghdl --std=08 -gFormal=true -gDepth=16 -gWidth=16 fifo.vhd vai_fifo.vhd -e vai_fifo
prep -top vai_fifo prep -top vai_fifo
#chformal -assume -remove vai_fifo/*
chformal -assume -remove vai_fifo/i_fifo
chformal -assume2assert vai_fifo/i_fifo %M
[files] [files]
../fifo/fifo.vhd ../fifo/fifo.vhd


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vai_fifo/vai_fifo.vhd View File

@ -72,8 +72,14 @@ begin
default clock is rising_edge(Clk_i); default clock is rising_edge(Clk_i);
-- Initial reset
RESTRICT_RESET : restrict
{not Reset_n_i[*3]; Reset_n_i[+]}[*1];
-- Inputs are low during reset for simplicity -- Inputs are low during reset for simplicity
vai_fifo_reset_a : assume always not Reset_n_i -> not Valid_i and not Accept_i;
ASSUME_INPUTS_DURING_RESET : assume always
not Reset_n_i ->
not Valid_i and not Accept_i;
end generate FormalG; end generate FormalG;


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