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Fix badge URL; minor further changes

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T. Meissner 3 years ago
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      README.md

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[![](https://img.shields.io/github/workflow/status/tmeissner/formal_hw_verification/Test/main?longCache=true&style=flat-square&label=Test&logo=GitHub%20Actions&logoColor=fff)](https://github.com/tmeissner/formal_hw_verification/actions?query=workflow%3ATest)
[![](https://img.shields.io/github/workflow/status/tmeissner/formal_hw_verification/Test/master?longCache=true&style=flat-square&label=Test&logo=GitHub%20Actions&logoColor=fff)](https://github.com/tmeissner/formal_hw_verification/actions?query=workflow%3ATest)
The original repository is located on my own git-server at [https://git.goodcleanfun.de/tmeissner/formal_hw_verification](https://git.goodcleanfun.de/tmeissner/formal_hw_verification) The original repository is located on my own git-server at [https://git.goodcleanfun.de/tmeissner/formal_hw_verification](https://git.goodcleanfun.de/tmeissner/formal_hw_verification)
@ -9,7 +9,7 @@ It is mirrored to github with every push, so both should be in sync.
Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with [SymbiYosys](https://github.com/YosysHQ/SymbiYosys), a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ/yosys). Tests and examples of using formal verification to check correctness of digital hardware designs. All tests are done with [SymbiYosys](https://github.com/YosysHQ/SymbiYosys), a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ/yosys).
All stuff in the master branch uses [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) and [GHDL](https://github.com/ghdl/ghdl) as VHDL front-end plugin for (Symbi)Yosys. Using GHDL as synthesis frontend allows using PSL as verification language. The alu, counter & vai_reg designs can be verified with that combination at the moment.
All stuff in the master branch uses [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) and [GHDL](https://github.com/ghdl/ghdl) as VHDL front-end plugin for (Symbi)Yosys. Using GHDL as synthesis frontend allows using PSL as verification language.
Some examples in the [verific branch](https://github.com/tmeissner/formal_hw_verification/tree/verific) use the commercial VHDL/SystemVerilog frontend plugin by Verific which isn't free SW and not included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information. Some examples in the [verific branch](https://github.com/tmeissner/formal_hw_verification/tree/verific) use the commercial VHDL/SystemVerilog frontend plugin by Verific which isn't free SW and not included in the free Yosys version. See on the [Symbiotic EDA website](https://www.symbioticeda.com) for more information.


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