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Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability

T. Meissner 3 months ago
parent
commit
ac767bb9d3
3 changed files with 37 additions and 26 deletions
  1. 13
    11
      alu/alu.vhd
  2. 13
    8
      alu/alu_t.sv
  3. 11
    7
      counter/counter_t.sv

+ 13
- 11
alu/alu.vhd View File

@@ -24,10 +24,12 @@ end entity alu;
24 24
 architecture rtl of alu is
25 25
 
26 26
 
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-  constant c_add : std_logic_vector(1 downto 0) := "00";
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-  constant c_sub : std_logic_vector(1 downto 0) := "01";
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-  constant c_and : std_logic_vector(1 downto 0) := "10";
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-  constant c_or  : std_logic_vector(1 downto 0) := "11";
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+  subtype t_opc is std_logic_vector(Opc_i'length-1 downto 0);
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+
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+  constant c_add : t_opc := "00";
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+  constant c_sub : t_opc := "01";
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+  constant c_and : t_opc := "10";
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+  constant c_or  : t_opc := "11";
31 33
 
32 34
 
33 35
 begin
@@ -40,14 +42,14 @@ begin
40 42
     elsif (rising_edge(Clk_i)) then
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       case Opc_i is
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         when c_add => (OverFlow_o, Dout_o) <=
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-	  std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) +
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-	                   resize(unsigned(DinB_i), Dout_o'length+1));
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+          std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) +
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+                           resize(unsigned(DinB_i), Dout_o'length+1));
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         when c_sub => (OverFlow_o, Dout_o) <=
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-	  std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) -
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-	                   resize(unsigned(DinB_i), Dout_o'length+1));
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-	when c_and => Dout_o <= DinA_i and DinB_i;
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-	when c_or  => Dout_o <= DinA_i or DinB_i;
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-	when others => null;
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+          std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) -
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+                           resize(unsigned(DinB_i), Dout_o'length+1));
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+        when c_and => Dout_o <= DinA_i and DinB_i;
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+        when c_or  => Dout_o <= DinA_i or DinB_i;
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+        when others => null;
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       end case;
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     end if;
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   end process;

+ 13
- 8
alu/alu_t.sv View File

@@ -41,24 +41,29 @@ module alu_t (
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   always @(posedge Clk_i)
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     init_state = 0;
43 43
 
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+  default clocking
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+    @(posedge Clk_i);
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+  endclocking
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+
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+  default disable iff (!Reset_n_i);
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+
44 50
 
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   bit unsigned [`WIDTH:0] dina, dinb;
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   assign dina = DinA_i;
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   assign dinb = DinB_i;
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == `OPC_ADD |=> Dout_o == ($past(DinA_i) + $past(DinB_i)));
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == `OPC_ADD && (dina + dinb) > 2**`WIDTH-1 |=> OverFlow_o);
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == `OPC_SUB |=> Dout_o == ($past(DinA_i) - $past(DinB_i)));
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == `OPC_SUB && (dina - dinb) > 2**`WIDTH-1 |=> OverFlow_o);
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == `OPC_AND |=> Dout_o == ($past(DinA_i) & $past(DinB_i)));
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Opc_i == `OPC_OR |=> Dout_o == ($past(DinA_i) | $past(DinB_i)));
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+  assert property (Opc_i == `OPC_ADD |=> Dout_o == ($past(DinA_i) + $past(DinB_i)));
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+  assert property (Opc_i == `OPC_ADD && (dina + dinb) > 2**`WIDTH-1 |=> OverFlow_o);
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+  assert property (Opc_i == `OPC_SUB |=> Dout_o == ($past(DinA_i) - $past(DinB_i)));
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+  assert property (Opc_i == `OPC_SUB && (dina - dinb) > 2**`WIDTH-1 |=> OverFlow_o);
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+  assert property (Opc_i == `OPC_AND |=> Dout_o == ($past(DinA_i) & $past(DinB_i)));
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+  assert property (Opc_i == `OPC_OR |=> Dout_o == ($past(DinA_i) | $past(DinB_i)));
56 62
 
57 63
 
58 64
 
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   property cover_opc (opc);
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-    @(posedge Clk_i)
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-      disable iff (!Reset_n_i) Opc_i == opc;
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+    Opc_i == opc;
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   endproperty
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   cover property (cover_opc(`OPC_ADD));

+ 11
- 7
counter/counter_t.sv View File

@@ -38,19 +38,23 @@ module counter_t (
38 38
 
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   // Use global clock to constrain the DUT clock
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   always @($global_clock) begin
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-    assume(Clk_i != $past(Clk_i));
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+    assume (Clk_i != $past(Clk_i));
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   end
43 43
 
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+  default clocking
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+    @(posedge Clk_i);
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+  endclocking
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+
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+  default disable iff (!Reset_n_i);
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+
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   // Immediate assertions
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   always @(*)
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     if (!Reset_n_i) assert (Data_o == `INITVAL);
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-  // Fails with unbounded prove using SMTBMC, maybe
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-  // the assumptions/assertions have to be more strict.
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-  // With abc pdr this can be successfully proved.
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Data_o <  `ENDVAL |=> Data_o == $past(Data_o) + 1);
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-  assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Data_o == `ENDVAL |=> $stable(Data_o));
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-  assert property (@(posedge Clk_i) Data_o >= `INITVAL && Data_o <= `ENDVAL);
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+  // Concurrent assertions
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+  assert property (Data_o <  `ENDVAL |=> Data_o == $past(Data_o) + 1);
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+  assert property (Data_o == `ENDVAL |=> $stable(Data_o));
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+  assert property (Data_o >= `INITVAL && Data_o <= `ENDVAL);
54 58
 
55 59
 
56 60
 endmodule