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Use PSL functions instead of workarounds; add forgotten always to asserts in alu

T. Meissner 3 months ago
parent
commit
f2f433b165
3 changed files with 30 additions and 63 deletions
  1. 17
    26
      alu/alu.vhd
  2. 3
    14
      counter/counter.vhd
  3. 10
    23
      vai_reg/vai_reg.vhd

+ 17
- 26
alu/alu.vhd View File

@@ -51,8 +51,8 @@ begin
51 51
         when c_sub =>
52 52
           v_result := std_logic_vector(unsigned('0' & DinA_i) -
53 53
                                        unsigned('0' & DinB_i));
54
-        when c_and => v_result := DinA_i and DinB_i;
55
-        when c_or  => v_result := DinA_i or  DinB_i;
54
+        when c_and => v_result := ('0', DinA_i and DinB_i);
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+        when c_or  => v_result := ('0', DinA_i or  DinB_i);
56 56
         when others => null;
57 57
       end case;
58 58
       Dout_o     <= v_result(Width-1 downto 0);
@@ -63,9 +63,6 @@ begin
63 63
 
64 64
   FormalG : if Formal generate
65 65
 
66
-    signal s_dina : std_logic_vector(DinA_i'range);
67
-    signal s_dinb : std_logic_vector(DinB_i'range);
68
-
69 66
     function max(a, b: std_logic_vector) return unsigned is
70 67
     begin
71 68
       if unsigned(a) > unsigned(b) then
@@ -77,42 +74,36 @@ begin
77 74
 
78 75
   begin
79 76
 
80
-    -- VHDL helper logic
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-    process is
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-    begin
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-      wait until rising_edge(Clk_i);
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-      s_dina <= DinA_i;
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-      s_dinb <= DinB_i;
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-    end process;
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-
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-
89 77
     default clock is rising_edge(Clk_i);
90 78
 
79
+    -- Initial reset
80
+    INITIAL_RESET : restrict {not Reset_n_i[*2]; Reset_n_i[+]}[*1];
81
+
91 82
     AFTER_RESET : assert always
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       not Reset_n_i -> Dout_o = (Dout_o'range => '0') and OverFlow_o = '0';
93 84
 
94
-    ADD_OP : assert Reset_n_i and Opc_i = c_add ->
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-      next unsigned(Dout_o) = unsigned(s_dina) + unsigned(s_dinb) abort not Reset_n_i;
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+    ADD_OP : assert always Reset_n_i and Opc_i = c_add ->
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+      next unsigned(Dout_o) = unsigned(prev(DinA_i)) + unsigned(prev(DinB_i)) abort not Reset_n_i;
96 87
 
97
-    SUB_OP : assert Reset_n_i and Opc_i = c_sub ->
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-      next unsigned(Dout_o) = unsigned(s_dina) - unsigned(s_dinb) abort not Reset_n_i;
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+    SUB_OP : assert always Reset_n_i and Opc_i = c_sub ->
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+      next unsigned(Dout_o) = unsigned(prev(DinA_i)) - unsigned(prev(DinB_i)) abort not Reset_n_i;
99 90
 
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-    AND_OP : assert Reset_n_i and Opc_i = c_and ->
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-      next Dout_o = (s_dina and s_dinb) abort not Reset_n_i;
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+    AND_OP : assert always Reset_n_i and Opc_i = c_and ->
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+      next Dout_o = (prev(DinA_i) and prev(DinB_i)) abort not Reset_n_i;
102 93
 
103
-    OR_OP :  assert Reset_n_i and Opc_i = c_or ->
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-      next Dout_o = (s_dina or s_dinb) abort not Reset_n_i;
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+    OR_OP :  assert always Reset_n_i and Opc_i = c_or ->
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+      next Dout_o = (prev(DinA_i) or prev(DinB_i)) abort not Reset_n_i;
105 96
 
106
-    OVERFLOW_ADD : assert Reset_n_i and Opc_i = c_add and (unsigned(DinA_i) + unsigned(DinB_i)) < max(DinA_i, DinB_i) ->
97
+    OVERFLOW_ADD : assert always Reset_n_i and Opc_i = c_add and (unsigned(DinA_i) + unsigned(DinB_i)) < max(DinA_i, DinB_i) ->
107 98
       next OverFlow_o abort not Reset_n_i;
108 99
 
109
-    NOT_OVERFLOW_ADD : assert Reset_n_i and Opc_i = c_add and (unsigned(DinA_i) + unsigned(DinB_i)) >= max(DinA_i, DinB_i) ->
100
+    NOT_OVERFLOW_ADD : assert always Reset_n_i and Opc_i = c_add and (unsigned(DinA_i) + unsigned(DinB_i)) >= max(DinA_i, DinB_i) ->
110 101
       next not OverFlow_o abort not Reset_n_i;
111 102
 
112
-    OVERFLOW_SUB : assert Reset_n_i and Opc_i = c_sub and (unsigned(DinA_i) - unsigned(DinB_i)) > unsigned(DinA_i) ->
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+    OVERFLOW_SUB : assert always Reset_n_i and Opc_i = c_sub and (unsigned(DinA_i) - unsigned(DinB_i)) > unsigned(DinA_i) ->
113 104
       next OverFlow_o abort not Reset_n_i;
114 105
 
115
-    NOT_OVERFLOW_SUB : assert Reset_n_i and Opc_i = c_sub and (unsigned(DinA_i) - unsigned(DinB_i)) <= unsigned(DinA_i) ->
106
+    NOT_OVERFLOW_SUB : assert always Reset_n_i and Opc_i = c_sub and (unsigned(DinA_i) - unsigned(DinB_i)) <= unsigned(DinA_i) ->
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       next not OverFlow_o abort not Reset_n_i;
117 108
 
118 109
   end generate FormalG;

+ 3
- 14
counter/counter.vhd View File

@@ -39,30 +39,19 @@ begin
39 39
 
40 40
   FormalG : if Formal generate
41 41
 
42
-    signal s_data : unsigned(Data_o'range);
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-
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-  begin
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-
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-    -- VHDL helper logic
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-    process is
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-    begin
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-      wait until rising_edge(Clk_i);
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-      s_data <= unsigned(Data_o);
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-    end process;
52
-
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     default clock is rising_edge(Clk_i);
54 43
 
55 44
     -- Initial reset
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-    INITIAL_RESET : restrict {Reset_n_i = '0'[*2]; Reset_n_i = '1'[+]}[*1];
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+    INITIAL_RESET : restrict {not Reset_n_i[*2]; Reset_n_i[+]}[*1];
57 46
 
58 47
     AFTER_RESET : assert always
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       not Reset_n_i -> Data_o = (Data_o'range => '0');
60 49
 
61 50
     COUNT_UP : assert always
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-      Reset_n_i and unsigned(Data_o) < to_unsigned(EndVal, 32) -> next unsigned(Data_o) = s_data + 1;
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+      Reset_n_i and unsigned(Data_o) < to_unsigned(EndVal, 32) -> next unsigned(Data_o) = unsigned(prev(Data_o)) + 1;
63 52
 
64 53
     END_VALUE : assert always
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-      unsigned(Data_o) = to_unsigned(EndVal, 32) -> next unsigned(Data_o) = s_data;
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+      unsigned(Data_o) = to_unsigned(EndVal, 32) -> next Data_o = prev(Data_o);
66 55
 
67 56
     VALID_RANGE : assert always
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       unsigned(Data_o) >= to_unsigned(InitVal, 32) and

+ 10
- 23
vai_reg/vai_reg.vhd View File

@@ -171,17 +171,6 @@ begin
171 171
     type t_cmd is (READ, WRITE, NOP);
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     signal s_cmd : t_cmd;
173 173
 
174
-    type t_vai is record
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-      Start  : std_logic;
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-      Stop   : std_logic;
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-      Data   : std_logic_vector(7 downto 0);
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-      Valid  : std_logic;
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-      Accept : std_logic;
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-    end record t_vai;
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-
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-    signal s_job_req : t_vai;
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-    signal s_job_ack : t_vai;
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-
185 174
 
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   begin
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@@ -190,8 +179,6 @@ begin
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     process is
191 180
     begin
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       wait until rising_edge(Clk_i);
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-      s_job_req <= (DinStart_i, DinStop_i, Din_i, DinValid_i, DinAccept_o);
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-      s_job_ack <= (DoutStart_o, DoutStop_o, Dout_o, DoutValid_o, DoutAccept_i);
195 182
       if (s_fsm_state = GET_HEADER) then
196 183
         if (DinValid_i = '1' and DinStart_i = '1') then
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           s_cmd  <= READ  when Din_i(3 downto 0) = x"0" else
@@ -208,26 +195,26 @@ begin
208 195
     -- RESTRICTIONS
209 196
 
210 197
     -- Initial reset
211
-    INITIAL_RESET : restrict {Reset_n_i = '0'[*2]; Reset_n_i = '1'[+]}[*1];
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+    INITIAL_RESET : restrict {not Reset_n_i[*2]; Reset_n_i[+]}[*1];
212 199
 
213 200
 
214 201
     -- CONSTRAINTS
215 202
 
216 203
     -- Valid stable until accepted
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     JOB_REQ_VALID_STABLE : assume always
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-      DinValid_i and not DinAccept_o -> next (DinValid_i until_ DinAccept_o);
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+      DinValid_i and not DinAccept_o -> next (stable(DinValid_i) until_ DinAccept_o);
219 206
 
220 207
     -- Start stable until accepted
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     JOB_REQ_START_STABLE : assume always
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-      DinValid_i and not DinAccept_o -> next (DinStart_i = s_job_req.Start until_ DinAccept_o);
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+      DinValid_i and not DinAccept_o -> next (stable(DinStart_i) until_ DinAccept_o);
223 210
 
224 211
     -- Stop stable until accepted
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     JOB_REQ_STOP_STABLE : assume always
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-      DinValid_i and not DinAccept_o -> next (DinStop_i = s_job_req.Stop until_ DinAccept_o);
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+      DinValid_i and not DinAccept_o -> next (stable(DinStop_i) until_ DinAccept_o);
227 214
 
228 215
     -- Data stable until accepted
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     JOB_REQ_DIN_STABLE : assume always
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-      DinValid_i and not DinAccept_o -> next (Din_i = s_job_req.Data until_ DinAccept_o);
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+      DinValid_i and not DinAccept_o -> next (stable(Din_i) until_ DinAccept_o);
231 218
 
232 219
 
233 220
     -- ASSERTIONS
@@ -315,19 +302,19 @@ begin
315 302
 
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      -- Valid has to be stable until accepted
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      JOB_ACK_VALID_STABLE : assert always
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-       DoutValid_o and not DoutAccept_i -> next (DoutValid_o until_ DoutAccept_i);
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+       DoutValid_o and not DoutAccept_i -> next (stable(DoutValid_o) until_ DoutAccept_i);
319 306
 
320 307
      -- Start has to be stable until accepted
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      JOB_ACK_START_STABLE : assert always
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-       DoutValid_o and not DoutAccept_i -> next (DoutStart_o = s_job_ack.Start until_ DoutAccept_i);
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+       DoutValid_o and not DoutAccept_i -> next (stable(DoutStart_o) until_ DoutAccept_i);
323 310
 
324 311
      -- Stop has to be stable until accepted
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      JOB_ACK_STOP_STABLE : assert always
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-       DoutValid_o and not DoutAccept_i -> next (DoutStop_o = s_job_ack.Stop until_ DoutAccept_i);
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+       DoutValid_o and not DoutAccept_i -> next (stable(DoutStop_o) until_ DoutAccept_i);
327 314
 
328 315
      -- Data has to be stable until accepted
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      JOB_ACK_DOUT_STABLE : assert always
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-       DoutValid_o and not DoutAccept_i -> next (Dout_o = s_job_ack.Data until_ DoutAccept_i);
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+       DoutValid_o and not DoutAccept_i -> next (stable(Dout_o) until_ DoutAccept_i);
331 318
 
332 319
     -- Data from selected address has to be read
333 320
     READ_DATA : assert always
@@ -352,7 +339,7 @@ begin
352 339
        DinValid_i and not DinStart_i and DinStop_i and not DinAccept_o [*];
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        DinValid_i and not DinStart_i and DinStop_i and DinAccept_o}
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       |=>
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-      {s_register(s_addr) = s_job_req.Data};
342
+      {s_register(s_addr) = prev(Din_i)};
356 343
 
357 344
 
358 345
     -- FUNCTIONAL COVERAGE