tmeissner
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formal_hw_verification
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2 Commits (195765a2aa640ba46ea9989e10e204d2b5de637e)

Author SHA1 Message Date
  T. Meissner 195765a2aa Adapt to use GHDL as plugin for Yosys VHDL synthesis 5 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 5 years ago