tmeissner
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formal_hw_verification
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4 Commits (3e621b02e940b1d5a5e7779561878b0d5792dcb6)

Author SHA1 Message Date
  T. Meissner 6c3a6db83b Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module 6 years ago
  T. Meissner 367343cff5 Add make targets and SymbiYosys tasks for cover, bmc & prove 6 years ago
  T. Meissner 195765a2aa Adapt to use GHDL as plugin for Yosys VHDL synthesis 6 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 7 years ago