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formal_hw_verification
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1 Commits (c355c144092ded32ec567cbbf11be0cab72855ed)

Author SHA1 Message Date
  T. Meissner 705171911a Add simple FIFO model incl. formal tests 4 years ago
  T. Meissner 6c3a6db83b Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module 5 years ago
  T. Meissner 367343cff5 Add make targets and SymbiYosys tasks for cover, bmc & prove 5 years ago
  T. Meissner 195765a2aa Adapt to use GHDL as plugin for Yosys VHDL synthesis 5 years ago
  T. Meissner 38ae7057c2 Incomment proof with abc pdr 6 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 6 years ago