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tmeissner
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formal_hw_verification
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verific
verific_problem
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5 Commits (f4029a24ec67c804f1a186fd73ffd93901bc2b2a)
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T. Meissner
bc59bfd47c
Symplifing Makefile targets
5 years ago
T. Meissner
6c3a6db83b
Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module
5 years ago
T. Meissner
367343cff5
Add make targets and SymbiYosys tasks for cover, bmc & prove
5 years ago
T. Meissner
195765a2aa
Adapt to use GHDL as plugin for Yosys VHDL synthesis
5 years ago
T. Meissner
a0f6a0b81d
Add simple VAI register file as base to try to formal verify FSM designs
6 years ago