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54 lines
1.3 KiB
54 lines
1.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity alu is
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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Opc_i : in std_logic_vector(1 downto 0);
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DinA_i : in std_logic_vector(31 downto 0);
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DinB_i : in std_logic_vector(31 downto 0);
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Dout_o : out std_logic_vector(31 downto 0);
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OverFlow_o : out std_logic
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);
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end entity alu;
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architecture rtl of alu is
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constant c_add : std_logic_vector(1 downto 0) := "00";
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constant c_sub : std_logic_vector(1 downto 0) := "01";
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constant c_and : std_logic_vector(1 downto 0) := "10";
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constant c_or : std_logic_vector(1 downto 0) := "11";
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begin
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process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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Dout_o <= (others => '0');
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elsif (rising_edge(Clk_i)) then
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case Opc_i is
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when c_add => (OverFlow_o, Dout_o) <=
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std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) +
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resize(unsigned(DinB_i), Dout_o'length+1));
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when c_sub => (OverFlow_o, Dout_o) <=
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std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) -
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resize(unsigned(DinB_i), Dout_o'length+1));
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when c_and => Dout_o <= DinA_i and DinB_i;
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when c_or => Dout_o <= DinA_i or DinB_i;
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when others => null;
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end case;
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end if;
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end process;
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end architecture rtl;
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