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42 lines
750 B
42 lines
750 B
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dlatch is
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generic (
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Init : std_logic_vector(31 downto 0) := x"DEADBEEF"
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);
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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Wen_i : in std_logic;
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Data_i : in std_logic_vector(15 downto 0);
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Data_o : out std_logic_vector(31 downto 0)
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);
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end entity dlatch;
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architecture rtl of dlatch is
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begin
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process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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Data_o <= Init;
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elsif (rising_edge(Clk_i)) then
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if (Wen_i = '1') then
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Data_o(7 downto 0) <= Data_i(7 downto 0);
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Data_o(23 downto 16) <= Data_i(15 downto 8);
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end if;
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end if;
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end process;
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end architecture rtl;
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