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121 lines
3.4 KiB
121 lines
3.4 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity alu is
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generic (
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Width : natural := 8;
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Formal : boolean := true
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);
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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Opc_i : in std_logic_vector(1 downto 0);
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DinA_i : in std_logic_vector(Width-1 downto 0);
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DinB_i : in std_logic_vector(Width-1 downto 0);
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Dout_o : out std_logic_vector(Width-1 downto 0);
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OverFlow_o : out std_logic
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);
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end entity alu;
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architecture rtl of alu is
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subtype t_opc is std_logic_vector(Opc_i'range);
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constant c_add : t_opc := "00";
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constant c_sub : t_opc := "01";
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constant c_and : t_opc := "10";
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constant c_or : t_opc := "11";
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begin
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process (Reset_n_i, Clk_i) is
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variable v_result : std_logic_vector(Width downto 0);
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begin
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if (Reset_n_i = '0') then
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v_result := (others => '0');
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Dout_o <= (others => '0');
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OverFlow_o <= '0';
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elsif (rising_edge(Clk_i)) then
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case Opc_i is
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when c_add =>
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v_result := std_logic_vector(unsigned('0' & DinA_i) +
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unsigned('0' & DinB_i));
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when c_sub =>
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v_result := std_logic_vector(unsigned('0' & DinA_i) -
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unsigned('0' & DinB_i));
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when c_and => v_result := DinA_i and DinB_i;
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when c_or => v_result := DinA_i or DinB_i;
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when others => null;
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end case;
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Dout_o <= v_result(Width-1 downto 0);
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OverFlow_o <= v_result(Width);
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end if;
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end process;
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FormalG : if Formal generate
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signal s_dina : std_logic_vector(DinA_i'range);
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signal s_dinb : std_logic_vector(DinB_i'range);
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function max(a, b: std_logic_vector) return unsigned is
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begin
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if unsigned(a) > unsigned(b) then
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return unsigned(a);
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else
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return unsigned(b);
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end if;
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end function max;
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begin
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-- VHDL helper logic
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process is
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begin
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wait until rising_edge(Clk_i);
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s_dina <= DinA_i;
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s_dinb <= DinB_i;
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end process;
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default clock is rising_edge(Clk_i);
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AFTER_RESET : assert always
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not Reset_n_i -> Dout_o = (Dout_o'range => '0') and OverFlow_o = '0';
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ADD_OP : assert Reset_n_i and Opc_i = c_add ->
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next unsigned(Dout_o) = unsigned(s_dina) + unsigned(s_dinb) abort not Reset_n_i;
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SUB_OP : assert Reset_n_i and Opc_i = c_sub ->
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next unsigned(Dout_o) = unsigned(s_dina) - unsigned(s_dinb) abort not Reset_n_i;
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AND_OP : assert Reset_n_i and Opc_i = c_and ->
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next Dout_o = (s_dina and s_dinb) abort not Reset_n_i;
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OR_OP : assert Reset_n_i and Opc_i = c_or ->
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next Dout_o = (s_dina or s_dinb) abort not Reset_n_i;
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OVERFLOW_ADD : assert Reset_n_i and Opc_i = c_add and (unsigned(DinA_i) + unsigned(DinB_i)) < max(DinA_i, DinB_i) ->
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next OverFlow_o abort not Reset_n_i;
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NOT_OVERFLOW_ADD : assert Reset_n_i and Opc_i = c_add and (unsigned(DinA_i) + unsigned(DinB_i)) >= max(DinA_i, DinB_i) ->
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next not OverFlow_o abort not Reset_n_i;
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OVERFLOW_SUB : assert Reset_n_i and Opc_i = c_sub and (unsigned(DinA_i) - unsigned(DinB_i)) > unsigned(DinA_i) ->
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next OverFlow_o abort not Reset_n_i;
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NOT_OVERFLOW_SUB : assert Reset_n_i and Opc_i = c_sub and (unsigned(DinA_i) - unsigned(DinB_i)) <= unsigned(DinA_i) ->
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next not OverFlow_o abort not Reset_n_i;
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end generate FormalG;
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end architecture rtl;
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