tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - alu/Makefile at 307c6b5f44c32062c8b36ad77a53a3bc97df8c19 - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

6 lines

80 B

Raw Blame History

 								alu: alu.vhd alu_t.sv alu_f.sby
 									sby -f -d work alu_f.sby
 								clean:
 									rm -rf work