tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - vai_reg/Makefile at 30ef1178238d45eda1035371d2171164e9c25c6b - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

6 lines

103 B

Raw Blame History

 								vai_reg: vai_reg.vhd properties.sv symbiyosys.sby
 									sby -f -d work symbiyosys.sby
 								clean:
 									rm -rf work