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169 lines
4.5 KiB
169 lines
4.5 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vai_reg is
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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-- req
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Din_i : in std_logic_vector(7 downto 0);
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DinValid_i : in std_logic;
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DinStart_i : in std_logic;
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DinStop_i : in std_logic;
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DinAccept_o : out std_logic;
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-- ack
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Dout_o : out std_logic_vector(7 downto 0);
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DoutValid_o : out std_logic;
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DoutStart_o : out std_logic;
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DoutStop_o : out std_logic;
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DoutAccept_i : in std_logic
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);
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end entity vai_reg;
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architecture rtl of vai_reg is
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constant C_READ : std_logic_vector(3 downto 0) := x"0";
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constant C_WRITE : std_logic_vector(3 downto 0) := x"1";
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type t_fsm_state is (IDLE, GET_HEADER, GET_DATA,
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SET_DATA, SEND_HEADER, SEND_DATA, SEND_FOOTER);
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signal s_fsm_state : t_fsm_state;
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type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
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signal s_register : t_register;
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signal s_header : std_logic_vector(7 downto 0);
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signal s_data : std_logic_vector(7 downto 0);
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signal s_error : boolean;
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signal s_dout_accepted : boolean;
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alias a_addr : std_logic_vector(3 downto 0) is s_header(7 downto 4);
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begin
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s_dout_accepted <= (DoutValid_o and DoutAccept_i) = '1';
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process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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DinAccept_o <= '0';
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DoutStart_o <= '0';
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DoutStop_o <= '0';
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DoutValid_o <= '0';
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Dout_o <= (others => '0');
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s_header <= (others => '0');
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s_data <= (others => '0');
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s_register <= (others => (others => '0'));
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s_error <= false;
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s_fsm_state <= IDLE;
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elsif (rising_edge(Clk_i)) then
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case s_fsm_state is
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when IDLE =>
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DinAccept_o <= '0';
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DoutStart_o <= '0';
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DoutStop_o <= '0';
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DoutValid_o <= '0';
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Dout_o <= (others => '0');
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s_header <= (others => '0');
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s_data <= (others => '0');
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s_error <= false;
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DinAccept_o <= '1';
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s_fsm_state <= GET_HEADER;
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when GET_HEADER =>
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if (DinValid_i = '1' and DinStart_i = '1') then
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s_header <= Din_i;
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if (Din_i(3 downto 0) = C_READ and DinStop_i = '1') then
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DinAccept_o <= '0';
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s_fsm_state <= GET_DATA;
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elsif (Din_i(3 downto 0) = C_WRITE and DinStop_i = '0') then
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s_fsm_state <= SET_DATA;
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else
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DinAccept_o <= '0';
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s_fsm_state <= IDLE;
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end if;
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end if;
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when GET_DATA =>
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if (unsigned(a_addr) <= 7) then
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s_data <= s_register(to_integer(unsigned(a_addr)));
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else
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s_error <= true;
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s_data <= (others => '0');
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end if;
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s_fsm_state <= SEND_HEADER;
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when SET_DATA =>
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if (DinValid_i = '1') then
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DinAccept_o <= '0';
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if (DinStop_i = '1') then
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if (unsigned(a_addr) <= 7) then
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s_register(to_integer(unsigned(a_addr))) <= Din_i;
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else
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s_error <= true;
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end if;
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s_fsm_state <= SEND_HEADER;
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else
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s_fsm_state <= IDLE;
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end if;
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end if;
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when SEND_HEADER =>
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DoutValid_o <= '1';
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DoutStart_o <= '1';
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Dout_o <= s_header;
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if (s_dout_accepted) then
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DoutValid_o <= '0';
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DoutStart_o <= '0';
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if (s_header(3 downto 0) = C_WRITE) then
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s_fsm_state <= SEND_FOOTER;
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else
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s_fsm_state <= SEND_DATA;
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end if;
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end if;
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when SEND_DATA =>
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DoutValid_o <= '1';
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Dout_o <= s_data;
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if (s_dout_accepted) then
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DoutValid_o <= '0';
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s_fsm_state <= SEND_FOOTER;
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end if;
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when SEND_FOOTER =>
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DoutValid_o <= '1';
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DoutStop_o <= '1';
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Dout_o <= x"01" when s_error else x"00";
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if (s_dout_accepted) then
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Dout_o <= (others => '0');
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DoutValid_o <= '0';
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DoutStop_o <= '0';
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s_fsm_state <= IDLE;
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end if;
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when others => null;
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end case;
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end if;
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end process;
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-- psl default clock is rising_edge(Clk_i);
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-- psl restrict {Reset_n_i = '0'[*5]; Reset_n_i = '1'[+]}[*1];
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-- psl assert always unsigned(a_addr) < 8;
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end architecture rtl;
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