formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs		4 years ago
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Makefile	Making counter design work with GHDL synthesis	5 years ago
counter.vhd	Replace reset checks by async VHDL asserts; Add assumptions about inputs	4 years ago
symbiyosys.sby	Replace reset checks by async VHDL asserts; Add assumptions about inputs	4 years ago