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332 lines
9.3 KiB
332 lines
9.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fifo is
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generic (
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Formal : boolean := true;
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Depth : positive := 16;
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Width : positive := 16
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);
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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-- write
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Wen_i : in std_logic;
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Din_i : in std_logic_vector(Width-1 downto 0);
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Full_o : out std_logic;
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Werror_o : out std_logic;
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-- read
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Ren_i : in std_logic;
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Dout_o : out std_logic_vector(Width-1 downto 0);
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Empty_o : out std_logic;
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Rerror_o : out std_logic
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);
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end entity fifo;
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architecture rtl of fifo is
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subtype t_fifo_pnt is natural range 0 to Depth-1;
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signal s_write_pnt : t_fifo_pnt;
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signal s_read_pnt : t_fifo_pnt;
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type t_fifo_mem is array (t_fifo_pnt'low to t_fifo_pnt'high) of std_logic_vector(Din_i'range);
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signal s_fifo_mem : t_fifo_mem;
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signal s_almost_full : boolean;
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signal s_almost_empty : boolean;
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function incr_pnt (data : t_fifo_pnt) return t_fifo_pnt is
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begin
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if (data = t_fifo_mem'high) then
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return 0;
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end if;
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return data + 1;
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end function incr_pnt;
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begin
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s_almost_full <= (s_write_pnt = s_read_pnt - 1) or
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(s_write_pnt = t_fifo_mem'high and s_read_pnt = t_fifo_mem'low);
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s_almost_empty <= (s_read_pnt = s_write_pnt - 1) or
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(s_read_pnt = t_fifo_mem'high and s_write_pnt = t_fifo_mem'low);
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WriteP : process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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s_write_pnt <= 0;
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Werror_o <= '0';
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elsif (rising_edge(Clk_i)) then
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Werror_o <= Wen_i and Full_o;
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if (Wen_i = '1' and Full_o = '0') then
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s_fifo_mem(s_write_pnt) <= Din_i;
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s_write_pnt <= incr_pnt(s_write_pnt);
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end if;
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end if;
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end process WriteP;
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ReadP : process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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s_read_pnt <= 0;
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Rerror_o <= '0';
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elsif (rising_edge(Clk_i)) then
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Rerror_o <= Ren_i and Empty_o;
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if (Ren_i = '1' and Empty_o = '0') then
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Dout_o <= s_fifo_mem(s_read_pnt);
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s_read_pnt <= incr_pnt(s_read_pnt);
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end if;
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end if;
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end process ReadP;
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FlagsP : process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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Full_o <= '0';
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Empty_o <= '1';
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elsif (rising_edge(Clk_i)) then
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if (Wen_i = '1') then
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if (Ren_i = '0' and s_almost_full) then
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Full_o <= '1';
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end if;
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Empty_o <= '0';
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end if;
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if (Ren_i = '1') then
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if (Wen_i = '0' and s_almost_empty) then
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Empty_o <= '1';
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end if;
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Full_o <= '0';
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end if;
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end if;
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end process FlagsP;
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FormalG : if Formal generate
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attribute anyconst : boolean;
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signal s_data : std_logic_vector(Width-1 downto 0);
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attribute anyconst of s_data : signal is true;
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signal s_cnt : natural range 0 to Depth;
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begin
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default clock is rising_edge(Clk_i);
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-- Initial reset
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RESTRICT_RESET : restrict
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{not Reset_n_i[*3]; Reset_n_i[+]}[*1];
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-- Inputs are low during reset for simplicity
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ASSUME_INPUTS_DURING_RESET : assume always
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not Reset_n_i ->
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not Wen_i and not Ren_i;
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-- Asynchronous (unclocked) Reset asserts
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FULL_RESET : process (all) is
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begin
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if (not Reset_n_i) then
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RESET_FULL : assert not Full_o;
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RESET_EMPTY : assert Empty_o;
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RESET_WERROR : assert not Werror_o;
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RESET_RERROR : assert not Rerror_o;
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RESET_WRITE_PNT : assert s_write_pnt = 0;
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RESET_READ_PNT : assert s_read_pnt = 0;
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end if;
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end process;
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-- No write pointer change when writing into full fifo
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WRITE_PNT_STABLE_WHEN_FULL : assert always
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Wen_i and Full_o ->
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next stable(s_write_pnt);
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-- No read pointer change when reading from empty fifo
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READ_PNT_STABLE_WHEN_EMPTY : assert always
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Ren_i and Empty_o ->
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next stable(s_read_pnt);
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-- Full when write and no read and write pointer ran up to read pointer
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FULL : assert always
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Wen_i and not Ren_i and
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(s_write_pnt = s_read_pnt - 1 or s_write_pnt = t_fifo_pnt'high and s_read_pnt = t_fifo_pnt'low) ->
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next Full_o;
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-- Not full when read
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NOT_FULL : assert always
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Ren_i ->
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next not Full_o;
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-- Empty when read and no write and read pointer ran up to write pointer
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EMPTY : assert always
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not Wen_i and Ren_i and
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(s_read_pnt = s_write_pnt - 1 or s_read_pnt = t_fifo_pnt'high and s_write_pnt = t_fifo_pnt'low) ->
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next Empty_o;
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-- Not empty when write
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NOT_EMPTY : assert always
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Wen_i ->
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next not Empty_o;
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-- Write error when writing into full fifo
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WERROR : assert always
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Wen_i and Full_o ->
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next Werror_o;
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-- No write error when fifo not full
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NO_WERROR : assert always
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not Full_o ->
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next not Werror_o;
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-- Read error when reading from empty fifo
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RERROR : assert always
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Ren_i and Empty_o ->
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next Rerror_o;
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-- No read error when fifo not empty
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NO_RERROR : assert always
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not Empty_o ->
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next not Rerror_o;
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-- Write pointer increment when writing into not full fifo
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-- and write pointer isn't at end value
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WRITE_PNT_INCR : assert always
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Wen_i and not Full_o and s_write_pnt /= t_fifo_pnt'high ->
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next s_write_pnt = prev(s_write_pnt) + 1;
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-- Write pointer wraparound when writing into not full fifo
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-- and write pointer is at end value
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WRITE_PNT_WRAP : assert always
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Wen_i and not Full_o and s_write_pnt = t_fifo_pnt'high ->
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next s_write_pnt = 0;
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-- Read pointer increment when reading from not empty fifo
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-- and read pointer isn't at end value
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READ_PNT_INCR : assert always
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Ren_i and not Empty_o and s_read_pnt /= t_fifo_pnt'high ->
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next s_read_pnt = prev(s_read_pnt) + 1;
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-- Read pointer wraparound when reading from not empty fifo
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-- and read pointer is at end value
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READ_PNT_WRAP : assert always
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Ren_i and not Empty_o and s_read_pnt = t_fifo_pnt'high ->
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next s_read_pnt = 0;
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-- Correct input data stored after valid write access
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DIN_VALID : assert always
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Wen_i and not Full_o ->
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next s_fifo_mem(s_write_pnt - 1) = prev(Din_i);
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-- Correct output data after valid read access
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DOUT_VALID : assert always
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Ren_i and not Empty_o ->
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next Dout_o = s_fifo_mem(s_read_pnt - 1);
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-- Fillstate calculation
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process (Clk_i) is
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begin
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if Reset_n_i = '0' then
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s_cnt <= 0;
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elsif rising_edge(Clk_i) then
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if Wen_i = '1' and Full_o = '0' and (Ren_i = '0' or Empty_o = '1') then
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s_cnt <= s_cnt + 1;
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elsif Ren_i = '1' and Empty_o = '0' and (Wen_i = '0' or Full_o = '1') then
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s_cnt <= s_cnt - 1;
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end if;
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end if;
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end process;
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-- Data flow checks
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-- GHDL only allows numerals in repetition operators
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-- so we have to use separate checks for each fill state
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DATA_FLOW_0 : assert always
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{{s_cnt = 0 and Wen_i = '1' and Din_i = s_data} ; {Ren_i[->1]}}
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|=> {Dout_o = s_data};
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DATA_FLOW_1 : assert always
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{{s_cnt = 1 and Wen_i = '1' and Din_i = s_data} : {Ren_i[->2]}}
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|=> {Dout_o = s_data};
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DATA_FLOW_2 : assert always
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{{s_cnt = 2 and Wen_i = '1' and Din_i = s_data} : {Ren_i[->3]}}
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|=> {Dout_o = s_data};
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DATA_FLOW_3 : assert always
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{{s_cnt = 3 and Wen_i = '1' and Din_i = s_data} : {Ren_i[->4]}}
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|=> {Dout_o = s_data};
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DATA_FLOW_4 : assert always
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{{s_cnt = 4 and Wen_i = '1' and Din_i = s_data} : {Ren_i[->5]}}
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|=> {Dout_o = s_data};
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DATA_FLOW_5 : assert always
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{{s_cnt = 5 and Wen_i = '1' and Din_i = s_data} : {Ren_i[->6]}}
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|=> {Dout_o = s_data};
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DATA_FLOW_6 : assert always
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{{s_cnt = 6 and Wen_i = '1' and Din_i = s_data} : {Ren_i[->7]}}
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|=> {Dout_o = s_data};
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DATA_FLOW_7 : assert always
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{{s_cnt = 7 and Wen_i = '1' and Din_i = s_data} : {Ren_i[->8]}}
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|=> {Dout_o = s_data};
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-- An alternative for GHDL: Replacing the [->] goto operator
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-- by counting Ren_i starting when s_data is written into fifo.
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-- The properties have to be slightly modified only.
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-- Sadly proving these needs much more (engine dependend) time than
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-- the separate checks above. I assume the counters are the reason.
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gen_data_checks : for i in 0 to Depth-1 generate
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begin
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GEN : if i = 0 generate
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DATA_FLOW_GEN : assert always
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{{s_cnt = i and Wen_i = '1' and Din_i = s_data} ; {not Ren_i[*]; Ren_i}}
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|=> {Dout_o = s_data};
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else generate
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signal s_ren_cnt : integer range -1 to i+1 := -1;
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begin
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process (Reset_n_i, Clk_i) is
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begin
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if not Reset_n_i then
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s_ren_cnt <= -1;
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elsif (rising_edge(Clk_i)) then
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if s_cnt = i and Wen_i = '1' and Din_i = s_data then
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s_ren_cnt <= 1 when Ren_i else 0;
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else
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s_ren_cnt <= s_ren_cnt + 1 when Ren_i = '1' and s_ren_cnt >= 0;
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end if;
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end if;
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end process;
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DATA_FLOW_GEN : assert always
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{{s_cnt = i and Wen_i = '1' and Din_i = s_data} : {Ren_i[*]; s_ren_cnt = i+1}}
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|-> {Dout_o = s_data};
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end generate GEN;
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end generate gen_data_checks;
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end generate FormalG;
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end architecture rtl;
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