Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 

30 lines
576 B

[tasks]
cover
bmc
prove
[options]
depth 20
cover: mode cover
bmc: mode bmc
prove: mode prove
[engines]
cover: smtbmc z3
bmc: abc bmc3
prove: abc pdr
[script]
ghdl --std=08 -gFormal=true -gDepth=8 -gWidth=4 fifo.vhd fwft_fifo.vhd -e fwft_fifo
prep -top fwft_fifo
# Convert all assumes to asserts in sub-units
chformal -assume2assert fwft_fifo/* %M
# Remove selected covers in i_fifo sub-unit as they cannot be reached
chformal -cover -remove */formalg.read_pnt_stable_when_empty.cover
chformal -cover -remove */formalg.rerror.cover
[files]
../fifo/fifo.vhd
fwft_fifo.vhd