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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/counter
T. Meissner 3c042a168b Remove unused Data_i port from testbench 6 years ago
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Makefile parameterize design; fix minor makefile problemswq 6 years ago
counter.vhd parameterize design; fix minor makefile problemswq 6 years ago
counter_f.sby Add counter as example for initial reset problems 6 years ago
counter_t.sv Remove unused Data_i port from testbench 6 years ago