tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - dlatchsr/Makefile at 445c013e5cbb9449b5c5bd0b5387b184a320e461 - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

7 lines

123 B

Raw Blame History

 								.PHONY: dlatch
 								dlatch: dlatch.vhd dlatch_t.sv dlatch_f.sby
 									sby -f -d work dlatch_f.sby
 								.PHONY: clean
 								clean:
 									rm -rf work