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76 lines
1.7 KiB
76 lines
1.7 KiB
`define WIDTH 8
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module alu_t (
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input Reset_n_i,
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input Clk_i,
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input [1:0] Opc_i,
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input [`WIDTH-1:0] DinA_i,
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input [`WIDTH-1:0] DinB_i,
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output [`WIDTH-1:0] Dout_o,
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output OverFlow_o
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);
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`define OPC_ADD 0
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`define OPC_SUB 1
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`define OPC_AND 2
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`define OPC_OR 3
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alu #(.Width(`WIDTH)) alu_i (
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.Reset_n_i(Reset_n_i),
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.Clk_i(Clk_i),
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.Opc_i(Opc_i),
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.DinA_i(DinA_i[`WIDTH-1:0]),
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.DinB_i(DinB_i[`WIDTH-1:0]),
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.Dout_o(Dout_o[`WIDTH-1:0]),
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.OverFlow_o(OverFlow_o)
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);
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reg init_state = 1;
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// Initial reset
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always @(*) begin
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if (init_state) assume (!Reset_n_i);
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if (!init_state) assume (Reset_n_i);
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end
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always @(posedge Clk_i)
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init_state = 0;
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default clocking
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@(posedge Clk_i);
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endclocking
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default disable iff (!Reset_n_i);
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bit unsigned [`WIDTH:0] dina, dinb;
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assign dina = DinA_i;
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assign dinb = DinB_i;
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assert property (Opc_i == `OPC_ADD |=> Dout_o == ($past(DinA_i) + $past(DinB_i)));
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assert property (Opc_i == `OPC_ADD && (dina + dinb) > 2**`WIDTH-1 |=> OverFlow_o);
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assert property (Opc_i == `OPC_SUB |=> Dout_o == ($past(DinA_i) - $past(DinB_i)));
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assert property (Opc_i == `OPC_SUB && (dina - dinb) > 2**`WIDTH-1 |=> OverFlow_o);
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assert property (Opc_i == `OPC_AND |=> Dout_o == ($past(DinA_i) & $past(DinB_i)));
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assert property (Opc_i == `OPC_OR |=> Dout_o == ($past(DinA_i) | $past(DinB_i)));
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property cover_opc (opc);
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Opc_i == opc;
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endproperty
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cover property (cover_opc(`OPC_ADD));
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cover property (cover_opc(`OPC_SUB));
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cover property (cover_opc(`OPC_AND));
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cover property (cover_opc(`OPC_OR));
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endmodule
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