Trying to verify Verilog/VHDL designs with formal methods and tools
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DUT := vai_reg
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.PHONY: cover prove all clean
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all: cover bmc prove
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cover: ${DUT}.vhd symbiyosys.sby
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sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@
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bmc: ${DUT}.vhd symbiyosys.sby
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sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@
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prove: ${DUT}.vhd symbiyosys.sby
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sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@
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clean:
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rm -rf work
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