tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - counter/counter_f.sby at 6d230226f26f43afda045b0fc1f6dbd6f69c51d0 - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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 								[options]
 								mode prove
 								multiclock on
 								[engines]
 								#smtbmc
 								abc pdr
 								[script]
 								verific -vhdl counter.vhd
 								verific -formal counter_t.sv
 								prep -top counter_t
 								[files]
 								counter.vhd
 								counter_t.sv