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55 lines
1.0 KiB
55 lines
1.0 KiB
module counter_t (
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input Reset_n_i,
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input Clk_i,
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output [31:0] Data_o
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);
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`define INITVAL 8
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`define ENDVAL 64
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counter #(
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.InitVal(`INITVAL),
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.EndVal(`ENDVAL)
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) counter_i (
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.Reset_n_i(Reset_n_i),
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.Clk_i(Clk_i),
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.Data_o(Data_o)
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);
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reg init_state = 1;
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// Initial reset
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always @(*) begin
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if (init_state) assume (!Reset_n_i);
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if (!init_state) assume (Reset_n_i);
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end
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always @(posedge Clk_i)
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init_state = 0;
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/*
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// Don't works with Verific at the moment
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initial begin
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assume (!Reset_n_i);
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end
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*/
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// Intermediate assertions
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always @(*)
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if (!Reset_n_i) assert (Data_o == `INITVAL);
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// Fails with unbounded prove using SMTBMC, maybe
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// the assumptions/assertions have to be more strict.
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// With abc pdr this can be successfully proved.
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Data_o < `ENDVAL |=> Data_o == $past(Data_o) + 1);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Data_o == `ENDVAL |=> $stable(Data_o));
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endmodule
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