tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - Makefile at 93e98010f715786c32760706ba45b80d16378d1e - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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 								DESIGNS := $(shell cat tests.txt)
 								.PHONY: ${DESIGNS} all clean
 								all: ${DESIGNS}
 								$(DESIGNS):
 									make -C $@ all -j$(nproc)
 								clean:
 									for dir in $(DESIGNS); do \
 									  make -C $$dir clean;    \
 									done