tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - vai_reg/Makefile at 93e98010f715786c32760706ba45b80d16378d1e - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

11 lines

205 B

Raw Blame History

 								DUT := vai_reg
 								.PHONY: cover bmc prove all clean
 								all: cover bmc prove
 								cover bmc prove: ${DUT}.vhd symbiyosys.sby
 									sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@
 								clean:
 									rm -rf work