tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - alu/alu_f.sby at 9d0198b0b48267c20d4dafabe07826528bde03e6 - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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 								[options]
 								mode prove
 								#mode bmc
 								#depth 20
 								[engines]
 								smtbmc
 								[script]
 								verific -vhdl alu.vhd
 								verific -formal alu_t.sv
 								prep -top alu_t
 								[files]
 								alu.vhd
 								alu_t.sv