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39 lines
716 B
39 lines
716 B
module counter_t (
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inout Reset_n_i,
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input Clk_i,
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input [31:0] Data_i,
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output [31:0] Data_o
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);
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counter counter_i (
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.Reset_n_i(Reset_n_i),
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.Clk_i(Clk_i),
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.Data_o(Data_o)
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);
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reg init_state;
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initial init_state = 1;
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always @(posedge Clk_i)
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init_state = 0;
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always @(*)
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assume (Reset_n_i == ~init_state);
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/*
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// Don't works with Verific at the moment
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initial begin
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assume (!Reset_n_i);
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end
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*/
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// Proves fail, counterexample hasn't initial reset active
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assert property (@(posedge Clk_i) Data_o >= 8 && Data_o <= 64);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i) Data_o < 64 |=> Data_o == $past(Data_o) + 1);
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endmodule
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