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98 lines
1.9 KiB
98 lines
1.9 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fwft_fifo is
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generic (
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Formal : boolean := true;
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Depth : positive := 16;
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Width : positive := 16
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);
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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-- write
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Wen_i : in std_logic;
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Din_i : in std_logic_vector(Width-1 downto 0);
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Full_o : out std_logic;
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Werror_o : out std_logic;
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-- read
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Ren_i : in std_logic;
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Dout_o : out std_logic_vector(Width-1 downto 0);
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Empty_o : out std_logic;
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Rerror_o : out std_logic
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);
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end entity fwft_fifo;
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architecture rtl of fwft_fifo is
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signal s_empty : std_logic;
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signal s_ren : std_logic;
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begin
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i_fifo : entity work.fifo
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generic map (
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Formal => Formal,
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Depth => Depth,
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Width => Width
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)
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port map (
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Reset_n_i => Reset_n_i,
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Clk_i => Clk_i,
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-- write
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Wen_i => Wen_i,
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Din_i => Din_i,
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Full_o => Full_o,
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Werror_o => Werror_o,
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-- read
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Ren_i => s_ren,
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Dout_o => Dout_o,
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Empty_o => s_empty,
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Rerror_o => open
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);
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s_ren <= not s_empty and (Empty_o or Ren_i);
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ReadFlagsP : process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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Empty_o <= '1';
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Rerror_o <= '0';
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elsif (rising_edge(Clk_i)) then
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Rerror_o <= Ren_i and Empty_o;
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if (s_ren = '1') then
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Empty_o <= '0';
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elsif (Ren_i = '1') then
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Empty_o <= '1';
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end if;
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end if;
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end process ReadFlagsP;
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FormalG : if Formal generate
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default clock is rising_edge(Clk_i);
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-- Initial reset
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RESTRICT_RESET : restrict
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{not Reset_n_i[*3]; Reset_n_i[+]}[*1];
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-- Inputs are low during reset for simplicity
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ASSUME_INPUTS_DURING_RESET : assume always
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not Reset_n_i ->
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not Wen_i and not Ren_i;
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end generate FormalG;
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end architecture rtl;
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