Trying to verify Verilog/VHDL designs with formal methods and tools
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{signal: [
{name: 'Reset_n_i', wave: '01..........'},
{name: 'Clk_i', wave: 'p...........'},
{},
{name: 's_fsm_state', wave: '2.2.22.2.2.2', data: ['IDLE', 'GET_HEADER', 'GET_DATA', 'SEND_HEADER', 'SEND_DATA', 'SEND_FOOTER', 'IDLE']},
{},
{name: 'Din_i', wave: 'x..3x.......', data: ['header']},
{name: 'DinStart_i', wave: '0..10.......'},
{name: 'DinStop_i', wave: '0..10.......'},
{name: 'DinValid_i', wave: '0..10.......'},
{name: 'DinAccept_o', wave: '0.1.0.......'},
{},
{name: 'Dout_o', wave: 'x....3.4.5.x', data: ['header', 'data', 'footer']},
{name: 'DoutStart_o', wave: '0....1.0....'},
{name: 'DoutStop_o', wave: '0........1.0'},
{name: 'DoutValid_o', wave: '0....1.....0'},
{name: 'DoutAccept_i', wave: '0.....101010'},
],
config: { hscale: 2 },
head:{
text:['tspan', {class:'h3'}, 'Read example (opcode 0x0)']
}
}