Trying to verify Verilog/VHDL designs with formal methods and tools
 
 
 

11 lines
205 B

DUT := vai_reg
.PHONY: cover bmc prove all clean
all: cover bmc prove
cover bmc prove: ${DUT}.vhd symbiyosys.sby
sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@
clean:
rm -rf work