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gatemate_experiments/blink/sim/Makefile

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Add blink design & simulation * blink should display incrementing binary numbers at LED1-LED8 of the GateMate FPGA Starter Kit. * Increment is done with circa 9.5 Hz
2 years ago
blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code
2 years ago
​
Add blink design & simulation * blink should display incrementing binary numbers at LED1-LED8 of the GateMate FPGA Starter Kit. * Increment is done with circa 9.5 Hz
2 years ago
blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code
2 years ago
Add blink design & simulation * blink should display incrementing binary numbers at LED1-LED8 of the GateMate FPGA Starter Kit. * Increment is done with circa 9.5 Hz
2 years ago
​
​
​
​
​
Adapt sim to updated RTL
2 years ago
​
blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code
2 years ago
Add blink design & simulation * blink should display incrementing binary numbers at LED1-LED8 of the GateMate FPGA Starter Kit. * Increment is done with circa 9.5 Hz
2 years ago
blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code
2 years ago
Add blink design & simulation * blink should display incrementing binary numbers at LED1-LED8 of the GateMate FPGA Starter Kit. * Increment is done with circa 9.5 Hz
2 years ago
blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code
2 years ago
Add blink design & simulation * blink should display incrementing binary numbers at LED1-LED8 of the GateMate FPGA Starter Kit. * Increment is done with circa 9.5 Hz
2 years ago
​
​
blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code
2 years ago
Add blink design & simulation * blink should display incrementing binary numbers at LED1-LED8 of the GateMate FPGA Starter Kit. * Increment is done with circa 9.5 Hz
2 years ago
​
​
​
​
​
Adapt sim to updated RTL
2 years ago
 
  1. DESIGN_NAME := blink
  2. LIB_SRC     := ../../lib/rtl_components.vhd ../../lib/sim_components.vhd
  3. RTL_SRC     := ../../lib/user_components.vhd ../rtl/${DESIGN_NAME}.vhd
  4. SIM_SRC     := tb_${DESIGN_NAME}.vhd
  5. SIM_FLAGS   := --std=08 -fpsl --workdir=work
  6. 

  7. .PHONY: all compile sim clean
  8. 

  9. all: sim
  10. compile: tb_${DESIGN_NAME}
  11. 

  12. tb_${DESIGN_NAME}: ${LIB_SRC} ${RTL_SRC} ${SIM_SRC} | work
  13. 	@echo "Analyze gatemate library ..."
  14. 	ghdl -a ${SIM_FLAGS} --work=gatemate ${LIB_SRC}
  15. 	@echo "Analyze testbench & design ..."
  16. 	ghdl -a ${SIM_FLAGS} -Pwork ${RTL_SRC} ${SIM_SRC}
  17. 	@echo "Elaborate testbench & design ..."
  18. 	ghdl -e ${SIM_FLAGS} -Pwork $@
  19. 

  20. sim: tb_${DESIGN_NAME}
  21. 	@echo "Run testbench ..."
  22. 	ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error  --wave=tb_${DESIGN_NAME}.ghw
  23. 

  24. work:
  25. 	mkdir $@
  26. 

  27. clean:
  28. 	@echo "Cleaning simulation files ..."
  29. 	rm -rf tb_${DESIGN_NAME} *.o work/