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Update neorv32_aes top level; Add some iverilog options

main
T. Meissner 1 year ago
parent
84f2515433
commit
b8d7ecd701
4 changed files with 1905 additions and 44 deletions
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  1. +31
    -13
      neorv32_aes/rtl/neorv32_aes.vhd
  2. +1832
    -0
      neorv32_aes/rtl/neorv32_top.vhd
  3. +8
    -6
      neorv32_aes/syn/Makefile
  4. +34
    -25
      neorv32_aes/syn/neorv32_aes.ccf

+ 31
- 13
neorv32_aes/rtl/neorv32_aes.vhd View File

@ -49,11 +49,11 @@ entity neorv32_aes is
clk_i : in std_logic; -- 10 MHz clock
rst_n_i : in std_logic; -- SW3 button
-- LED outputs
led_n_o : out std_logic_vector(7 downto 0)
led_n_o : out std_logic_vector(7 downto 0);
-- UART0
-- uart_rx_i : in std_logic; -- PMODA IO
-- uart_tx_o : out std_logic -- PMODA IO
debug_o : out std_logic_vector(15 downto 0)
);
end entity;
@ -67,9 +67,12 @@ architecture rtl of neorv32_aes is
signal s_pll_clk : std_logic;
signal s_cfg_end : std_logic;
signal s_rst_n : std_logic;
signal s_rst_n : std_logic;
signal s_rst_debounced : std_logic;
signal s_con_gpio : std_ulogic_vector(63 downto 0);
signal s_debug : std_logic_vector(63 downto 0);
begin
@ -98,16 +101,30 @@ begin
CFG_END => s_cfg_end
);
s_rst_n <= s_pll_lock and s_cfg_end and rst_n_i;
rst_debounce : block is
signal s_rst_d : std_logic_vector(29 downto 0);
begin
process (s_pll_clk, rst_n_i) is
begin
if (not rst_n_i) then
s_rst_d <= (others => '0');
elsif (rising_edge(s_pll_clk)) then
s_rst_d <= s_rst_d(s_rst_d'left-1 downto 0) & rst_n_i;
end if;
end process;
s_rst_debounced <= and s_rst_d;
end block rst_debounce;
s_rst_n <= s_pll_lock and s_cfg_end and s_rst_debounced;
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity neorv32.neorv32_top
generic map (
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of s_pll_clk in Hz
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_C => false, -- implement compressed extension?
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?
@ -116,9 +133,9 @@ begin
FAST_SHIFT_EN => false,
-- Internal Instruction memory --
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_SIZE => 4*1024, --16*1024, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
@ -134,17 +151,18 @@ begin
-- GPIO
gpio_o => s_con_gpio,
-- primary UART0
uart0_txd_o => open,
uart0_rxd_i => '0'
uart0_txd_o => open, -- uart_tx_o,
uart0_rxd_i => '1', -- uart_rx_i,
-- debug
debug_o => s_debug
);
debug_o <= s_debug(15 downto 0);
-- p_r ERROR when connecting uart_rx_i & yosys option -retime (with both Yosys inferred & instantiated CC_BRAM_40K or CC_BRAM_40K memory)
-- FATAL ERROR: RAM 4070 Output DOA[6] not used but Input DIA[6] used!
-- program finished with exit code: 2
-- p_r ERROR with FAST_MUL_EN (fix with suggested p_r option switched off)
-- FATAL ERROR: CP-lines in Multiplier cannot be used for CLK; please switch off using CP-lines for CLK (-cCP)
-- IO Connection --------------------------------------------------------------------------
led_n_o <= not std_logic_vector(s_con_gpio(7 downto 0));


+ 1832
- 0
neorv32_aes/rtl/neorv32_top.vhd
File diff suppressed because it is too large
View File


+ 8
- 6
neorv32_aes/syn/Makefile View File

@ -11,7 +11,7 @@ NEORV32_MEM_ENTITIES := \
NEORV32_MEM_SRC := \
$(NEORV32_CORE_DIR)/mem/neorv32_imem.default.vhd \
$(NEORV32_CORE_DIR)/mem/neorv32_dmem.default.vhd
$(NEORV32_CORE_DIR)/mem/neorv32_dmem.gatemate.vhd
NEORV32_CORE_SRC := \
$(NEORV32_CORE_DIR)/neorv32_bootloader_image.vhd \
@ -51,7 +51,8 @@ NEORV32_CORE_SRC := \
$(NEORV32_CORE_DIR)/neorv32_xirq.vhd \
$(NEORV32_CORE_DIR)/neorv32_cfs.vhd \
$(NEORV32_CORE_DIR)/neorv32_cfs_aes.vhd \
$(NEORV32_CORE_DIR)/neorv32_top.vhd
../rtl/neorv32_top.vhd
# $(NEORV32_CORE_DIR)/neorv32_top.vhd
NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} \
${NEORV32_MEM_SRC} ${NEORV32_CORE_SRC}
@ -69,8 +70,9 @@ WORK_FILES := ../rtl/${DESIGN_NAME}.vhd
GM_FILES := ../../lib/rtl_components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8
# -retime
ICARUSFLAGS := -Wall -Winfloop -g2012 -gspecify -Ttyp
YOSYSPIPE := -nomx8 -nobram
PNRFLAGS := -om 3 -cCP on
PNRTOOL := $(shell which p_r)
@ -107,12 +109,12 @@ ${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
# Post-synthesis simulation target
syn_sim: ${DESIGN_NAME}.v
iverilog -g2012 -o tb_${DESIGN_NAME}_syn.vvp ${DESIGN_NAME}.v tb_${DESIGN_NAME}.v /usr/local/share/yosys/gatemate/cells_sim.v
iverilog ${ICARUSFLAGS} -o tb_${DESIGN_NAME}_syn.vvp ${DESIGN_NAME}.v tb_${DESIGN_NAME}.v /usr/local/share/yosys/gatemate/cells_sim.v
vvp -N tb_${DESIGN_NAME}_syn.vvp -fst
# Post-implementation simulation target
imp_sim: ${DESIGN_NAME}.bit
iverilog -g2012 -o tb_${DESIGN_NAME}_imp.vvp build/${DESIGN_NAME}_00.v tb_${DESIGN_NAME}.v /opt/cc-toolchain-linux/bin/p_r/cpelib.v
iverilog ${ICARUSFLAGS} -o tb_${DESIGN_NAME}_imp.vvp build/${DESIGN_NAME}_00.v tb_${DESIGN_NAME}.v /opt/cc-toolchain-linux/bin/p_r/cpelib.v
vvp -N tb_${DESIGN_NAME}_imp.vvp -fst
# FPGA FW load per JTAG


+ 34
- 25
neorv32_aes/syn/neorv32_aes.ccf View File

@ -1,25 +1,34 @@
# Configuration for the Gatemate eval board
Pin_in "clk_i" Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;
Pin_in "rst_n_i" Loc = "IO_EB_B0"; # SW3
Pin_out "led_n_o[0]" Loc = "IO_EB_B1"; # LED D1
Pin_out "led_n_o[1]" Loc = "IO_EB_B2"; # LED D2
Pin_out "led_n_o[2]" Loc = "IO_EB_B3"; # LED D3
Pin_out "led_n_o[3]" Loc = "IO_EB_B4"; # LED D4
Pin_out "led_n_o[4]" Loc = "IO_EB_B5"; # LED D5
Pin_out "led_n_o[5]" Loc = "IO_EB_B6"; # LED D6
Pin_out "led_n_o[6]" Loc = "IO_EB_B7"; # LED D7
Pin_out "led_n_o[7]" Loc = "IO_EB_B8"; # LED D8
#Pin_in "uart_rx_i" Loc = "IO_NB_A1"; # PMODA IO3
#Pin_out "uart_tx_o" Loc = "IO_NB_A0"; # PMODA IO1
#
#Pin_out "debug_o[0]" Loc = "IO_NB_A4";
#Pin_out "debug_o[1]" Loc = "IO_NB_A5";
#Pin_out "debug_o[2]" Loc = "IO_NB_A6";
#Pin_out "debug_o[3]" Loc = "IO_NB_A7";
#Pin_out "debug_o[4]" Loc = "IO_NB_B4";
#Pin_out "debug_o[5]" Loc = "IO_NB_B5";
#Pin_out "debug_o[6]" Loc = "IO_NB_B6";
#Pin_out "debug_o[7]" Loc = "IO_NB_B7";
# Configuration for the Gatemate eval board
Pin_in "clk_i" Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;
Pin_in "rst_n_i" Loc = "IO_EB_B0"; # SW3
Pin_out "led_n_o[0]" Loc = "IO_EB_B1"; # LED D1
Pin_out "led_n_o[1]" Loc = "IO_EB_B2"; # LED D2
Pin_out "led_n_o[2]" Loc = "IO_EB_B3"; # LED D3
Pin_out "led_n_o[3]" Loc = "IO_EB_B4"; # LED D4
Pin_out "led_n_o[4]" Loc = "IO_EB_B5"; # LED D5
Pin_out "led_n_o[5]" Loc = "IO_EB_B6"; # LED D6
Pin_out "led_n_o[6]" Loc = "IO_EB_B7"; # LED D7
Pin_out "led_n_o[7]" Loc = "IO_EB_B8"; # LED D8
#Pin_in "uart_rx_i" Loc = "IO_NB_A1"; # PMODA IO3
#Pin_out "uart_tx_o" Loc = "IO_NB_A0"; # PMODA IO1
#
Pin_out "debug_o[0]" Loc = "IO_NB_A4";
Pin_out "debug_o[1]" Loc = "IO_NB_A5";
Pin_out "debug_o[2]" Loc = "IO_NB_A6";
Pin_out "debug_o[3]" Loc = "IO_NB_A7";
Pin_out "debug_o[4]" Loc = "IO_NB_B4";
Pin_out "debug_o[5]" Loc = "IO_NB_B5";
Pin_out "debug_o[6]" Loc = "IO_NB_B6";
Pin_out "debug_o[7]" Loc = "IO_NB_B7";
Pin_out "debug_o[8]" Loc = "IO_NB_A0";
Pin_out "debug_o[9]" Loc = "IO_NB_A1";
Pin_out "debug_o[10]" Loc = "IO_NB_A2";
Pin_out "debug_o[11]" Loc = "IO_NB_A3";
Pin_out "debug_o[12]" Loc = "IO_NB_B0";
Pin_out "debug_o[13]" Loc = "IO_NB_B1";
Pin_out "debug_o[14]" Loc = "IO_NB_B2";
Pin_out "debug_o[15]" Loc = "IO_NB_B3";

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