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@ -49,11 +49,11 @@ entity neorv32_aes is |
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clk_i : in std_logic; -- 10 MHz clock |
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rst_n_i : in std_logic; -- SW3 button |
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-- LED outputs |
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led_n_o : out std_logic_vector(7 downto 0) |
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led_n_o : out std_logic_vector(7 downto 0); |
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-- UART0 |
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-- uart_rx_i : in std_logic; -- PMODA IO |
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-- uart_tx_o : out std_logic -- PMODA IO |
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debug_o : out std_logic_vector(15 downto 0) |
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); |
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end entity; |
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@ -67,9 +67,12 @@ architecture rtl of neorv32_aes is |
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signal s_pll_clk : std_logic; |
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signal s_cfg_end : std_logic; |
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signal s_rst_n : std_logic; |
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signal s_rst_n : std_logic; |
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signal s_rst_debounced : std_logic; |
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signal s_con_gpio : std_ulogic_vector(63 downto 0); |
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signal s_debug : std_logic_vector(63 downto 0); |
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begin |
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@ -98,16 +101,30 @@ begin |
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CFG_END => s_cfg_end |
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); |
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s_rst_n <= s_pll_lock and s_cfg_end and rst_n_i; |
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rst_debounce : block is |
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signal s_rst_d : std_logic_vector(29 downto 0); |
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begin |
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process (s_pll_clk, rst_n_i) is |
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begin |
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if (not rst_n_i) then |
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s_rst_d <= (others => '0'); |
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elsif (rising_edge(s_pll_clk)) then |
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s_rst_d <= s_rst_d(s_rst_d'left-1 downto 0) & rst_n_i; |
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end if; |
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end process; |
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s_rst_debounced <= and s_rst_d; |
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end block rst_debounce; |
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s_rst_n <= s_pll_lock and s_cfg_end and s_rst_debounced; |
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-- The core of the problem ---------------------------------------------------------------- |
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-- ------------------------------------------------------------------------------------------- |
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neorv32_inst: entity neorv32.neorv32_top |
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generic map ( |
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of s_pll_clk in Hz |
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INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM |
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INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM |
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-- RISC-V CPU Extensions -- |
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
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CPU_EXTENSION_RISCV_C => false, -- implement compressed extension? |
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CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? |
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? |
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CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? |
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@ -116,9 +133,9 @@ begin |
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FAST_SHIFT_EN => false, |
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-- Internal Instruction memory -- |
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MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory |
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MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes |
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MEM_INT_IMEM_SIZE => 4*1024, --16*1024, -- size of processor-internal instruction memory in bytes |
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-- Internal Data memory -- |
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MEM_INT_DMEM_EN => true, -- implement processor-internal data memory |
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MEM_INT_DMEM_EN => true, -- implement processor-internal data memory |
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes |
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-- Processor peripherals -- |
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? |
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@ -134,17 +151,18 @@ begin |
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-- GPIO |
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gpio_o => s_con_gpio, |
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-- primary UART0 |
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uart0_txd_o => open, |
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uart0_rxd_i => '0' |
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uart0_txd_o => open, -- uart_tx_o, |
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uart0_rxd_i => '1', -- uart_rx_i, |
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-- debug |
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debug_o => s_debug |
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); |
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debug_o <= s_debug(15 downto 0); |
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-- p_r ERROR when connecting uart_rx_i & yosys option -retime (with both Yosys inferred & instantiated CC_BRAM_40K or CC_BRAM_40K memory) |
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-- FATAL ERROR: RAM 4070 Output DOA[6] not used but Input DIA[6] used! |
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-- program finished with exit code: 2 |
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-- p_r ERROR with FAST_MUL_EN (fix with suggested p_r option switched off) |
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-- FATAL ERROR: CP-lines in Multiplier cannot be used for CLK; please switch off using CP-lines for CLK (-cCP) |
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-- IO Connection -------------------------------------------------------------------------- |
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led_n_o <= not std_logic_vector(s_con_gpio(7 downto 0)); |
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