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@ -4,8 +4,6 @@ AES_DIR := ../../cryptocores/aes/rtl/vhdl |
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CRYPTO_SRC := \
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$(AES_DIR)/aes_pkg.vhd \
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$(AES_DIR)/aes_enc.vhd \
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$(AES_DIR)/aes_dec.vhd \
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$(AES_DIR)/aes.vhd \
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$(AES_DIR)/../../../ctraes/rtl/vhdl/ctraes.vhd |
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WORK_FILES := \
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@ -21,8 +19,15 @@ GHDL_FLAGS := --std=08 --workdir=build -Pbuild |
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ICARUSFLAGS := -Wall -Winfloop -g2012 -gspecify -Ttyp |
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YOSYSPIPE := -nomx8 |
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PNRFLAGS := -om 3 -cCP on |
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# yosys -nomx8 option has to be used as GM FPGA hasn't any (working?) MUX8 cells (in contrast to documentation)
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# yosys -retime option causes design AES unit misbehavior (wrong results)
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# yosys -dff option can be used without risk (but leads to 2.5 mhz less fmax)
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PNRTOOL := $(shell which p_r) |
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PNRFLAGS := -om 3 -cCP off |
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# p_r +cCP option causes design AES unit misbehavior (wrong results != retime results)
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# p_r +sp option causes design AES unit misbehavior (wrong results != retime results != cCP results)
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# p_r +cCP with +gCP also breaks UART
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.PHONY: all syn imp prog syn_sim imp_sim |
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