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@ -36,6 +36,9 @@ library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use ieee.numeric_std.all; |
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library neorv32; |
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use neorv32.neorv32_package.all; |
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library gatemate; |
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library gatemate; |
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use gatemate.components.all; |
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use gatemate.components.all; |
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@ -46,17 +49,18 @@ entity neorv32_aes is |
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clk_i : in std_logic; -- 10 MHz clock |
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clk_i : in std_logic; -- 10 MHz clock |
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rst_n_i : in std_logic; -- SW3 button |
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rst_n_i : in std_logic; -- SW3 button |
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-- LED outputs |
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-- LED outputs |
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led_n_o : out std_logic_vector(7 downto 0); |
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led_n_o : out std_logic_vector(7 downto 0) |
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-- UART0 |
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-- UART0 |
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uart_rx_i : in std_logic; -- PMODA IO |
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uart_tx_o : out std_logic -- PMODA IO |
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-- uart_rx_i : in std_logic; -- PMODA IO |
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-- uart_tx_o : out std_logic -- PMODA IO |
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); |
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); |
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end entity; |
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end entity; |
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architecture rtl of neorv32_aes is |
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architecture rtl of neorv32_aes is |
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-- configuration -- |
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-- configuration -- |
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constant f_clock_c : natural := 20_000_000; -- clock frequency in Hz |
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constant f_clock_c : natural := 10_000_000; -- clock frequency in Hz |
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-- Globals |
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-- Globals |
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signal s_pll_lock : std_logic; |
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signal s_pll_lock : std_logic; |
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@ -65,14 +69,14 @@ architecture rtl of neorv32_aes is |
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signal s_rst_n : std_logic; |
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signal s_rst_n : std_logic; |
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signal s_con_gpio : std_logic_vector(3 downto 0); |
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signal s_con_gpio : std_ulogic_vector(63 downto 0); |
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begin |
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begin |
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PLL : CC_PLL |
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PLL : CC_PLL |
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generic map ( |
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generic map ( |
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REF_CLK => "10", |
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REF_CLK => "10", |
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OUT_CLK => "20", |
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OUT_CLK => "10", |
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PERF_MD => "SPEED" |
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PERF_MD => "SPEED" |
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) |
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) |
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port map ( |
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port map ( |
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@ -98,18 +102,30 @@ begin |
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-- The core of the problem ---------------------------------------------------------------- |
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-- The core of the problem ---------------------------------------------------------------- |
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-- ------------------------------------------------------------------------------------------- |
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-- ------------------------------------------------------------------------------------------- |
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neorv32_inst: entity work.neorv32_top |
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neorv32_inst: entity neorv32.neorv32_top |
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generic map ( |
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generic map ( |
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of s_pll_clk in Hz |
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CPU_EXTENSION_RISCV_M => true, |
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FAST_MUL_EN => false, |
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FAST_SHIFT_EN => false, |
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MEM_INT_IMEM_SIZE => 8*1024, |
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MEM_INT_DMEM_SIZE => 16*1024, |
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IO_MTIME_EN => false, |
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IO_WDT_EN => false, |
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IO_TRNG_EN => false, |
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IO_CFS_EN => true |
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of s_pll_clk in Hz |
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INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM |
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-- RISC-V CPU Extensions -- |
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
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CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension? |
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? |
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CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? |
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-- Tuning Options -- |
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FAST_MUL_EN => false, |
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FAST_SHIFT_EN => false, |
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-- Internal Instruction memory -- |
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MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory |
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MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes |
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-- Internal Data memory -- |
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MEM_INT_DMEM_EN => true, -- implement processor-internal data memory |
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes |
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-- Processor peripherals -- |
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? |
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)? |
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IO_UART0_EN => false, -- implement primary universal asynchronous receiver/transmitter (UART0)? |
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IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? |
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IO_AES_EN => true -- implement AES(128) custom function? |
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) |
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) |
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port map ( |
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port map ( |
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-- Global control -- |
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-- Global control -- |
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@ -118,21 +134,18 @@ begin |
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-- GPIO |
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-- GPIO |
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gpio_o => s_con_gpio, |
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gpio_o => s_con_gpio, |
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-- primary UART0 |
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-- primary UART0 |
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uart_txd_o => uart_tx_o, |
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uart_rxd_i => uart_rx_i |
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uart0_txd_o => open, |
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uart0_rxd_i => '0' |
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); |
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); |
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-- p_r ERROR when connecting uart_rx_i & yosys option -retime (with both Yosys inferred & instantiated CC_BRAM_40K or CC_BRAM_40K memory) |
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-- p_r ERROR when connecting uart_rx_i & yosys option -retime (with both Yosys inferred & instantiated CC_BRAM_40K or CC_BRAM_40K memory) |
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-- FATAL ERROR: RAM 4070 Output DOA[6] not used but Input DIA[6] used! |
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-- FATAL ERROR: RAM 4070 Output DOA[6] not used but Input DIA[6] used! |
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-- program finished with exit code: 2 |
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-- program finished with exit code: 2 |
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-- p_r ERROR with FAST_MUL_EN (even with the suggested p_r option sitched off) |
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-- p_r ERROR with FAST_MUL_EN (fix with suggested p_r option switched off) |
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-- FATAL ERROR: CP-lines in Multiplier cannot be used for CLK; please switch off using CP-lines for CLK (-cCP) |
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-- FATAL ERROR: CP-lines in Multiplier cannot be used for CLK; please switch off using CP-lines for CLK (-cCP) |
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-- IO Connection -------------------------------------------------------------------------- |
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-- IO Connection -------------------------------------------------------------------------- |
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-- ------------------------------------------------------------------------------------------- |
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led_n_o(3 downto 0) <= s_con_gpio; |
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led_n_o(7 downto 4) <= (others => '1'); |
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-- uart_tx_o <= uart_rx_i; |
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led_n_o <= not std_logic_vector(s_con_gpio(7 downto 0)); |
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end architecture; |
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end architecture; |