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Add CC_BRAM_20K and CC_BRAM_40K to rtl components package

main
T. Meissner 2 years ago
parent
4cc4aa25e2
commit
ee77f92bd3
1 changed files with 303 additions and 0 deletions
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      lib/rtl_components.vhd

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lib/rtl_components.vhd View File

@ -127,6 +127,309 @@ package components is
);
end component;
component CC_BRAM_20K is
generic (
-- Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
LOC : string := "UNPLACED";
-- Port Widths
A_RD_WIDTH : natural := 0;
B_RD_WIDTH : natural := 0;
A_WR_WIDTH : natural := 0;
B_WR_WIDTH : natural := 0;
-- RAM and Write Modes
RAM_MODE : string := "SDP";
A_WR_MODE : string := "NO_CHANGE";
B_WR_MODE : string := "NO_CHANGE";
-- Inverting Control Pins
A_CLK_INV : std_logic := '0';
B_CLK_INV : std_logic := '0';
A_EN_INV : std_logic := '0';
B_EN_INV : std_logic := '0';
A_WE_INV : std_logic := '0';
B_WE_INV : std_logic := '0';
-- Output Register
A_DO_REG : std_logic := '0';
B_DO_REG : std_logic := '0';
-- Error Checking and Correction
ECC_EN : std_logic := '0';
-- RAM init content
INIT_00 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
port (
-- clocks
A_CLK : in std_logic;
B_CLK : in std_logic;
-- inputs
A_EN : in std_logic;
B_EN : in std_logic;
A_WE : in std_logic;
B_WE : in std_logic;
A_ADDR : in std_logic_vector(15 downto 0);
B_ADDR : in std_logic_vector(15 downto 0);
A_DI : in std_logic_vector(19 downto 0);
B_DI : in std_logic_vector(19 downto 0);
A_BM : in std_logic_vector(19 downto 0);
B_BM : in std_logic_vector(19 downto 0);
-- outputs
A_DO : out std_logic_vector(19 downto 0);
B_DO : out std_logic_vector(19 downto 0);
ECC_1B_ERR : out std_logic;
ECC_2B_ERR : out std_logic
);
end component;
component CC_BRAM_40K is
generic (
-- Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
LOC : string := "UNPLACED";
CAS : string := "NONE"; -- NONE, UPPER, LOWER
-- Port Widths
A_RD_WIDTH : natural := 0;
B_RD_WIDTH : natural := 0;
A_WR_WIDTH : natural := 0;
B_WR_WIDTH : natural := 0;
-- RAM and Write Modes
RAM_MODE : string := "SDP";
A_WR_MODE : string := "NO_CHANGE";
B_WR_MODE : string := "NO_CHANGE";
-- Inverting Control Pins
A_CLK_INV : std_logic := '0';
B_CLK_INV : std_logic := '0';
A_EN_INV : std_logic := '0';
B_EN_INV : std_logic := '0';
A_WE_INV : std_logic := '0';
B_WE_INV : std_logic := '0';
-- Output Register
A_DO_REG : std_logic := '0';
B_DO_REG : std_logic := '0';
-- Error Checking and Correction
A_ECC_EN : std_logic := '0';
B_ECC_EN : std_logic := '0';
-- RAM init content
INIT_00 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_40 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_41 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_42 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_43 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_44 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_45 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_46 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_47 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_48 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_49 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_4A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_4B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_4C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_4D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_4E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_4F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_50 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_51 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_52 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_53 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_54 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_55 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_56 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_57 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_58 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_59 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_5A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_5B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_5C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_5D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_5E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_5F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_60 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_61 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_62 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_63 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_64 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_65 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_66 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_67 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_68 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_69 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_6A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_6B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_6C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_6D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_6E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_6F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_70 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_71 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_72 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_73 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_74 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_75 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_76 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_77 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_78 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_79 : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_7A : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_7B : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_7C : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_7D : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_7E : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000";
INIT_7F : std_logic_vector(319 downto 0) := x"00000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
port (
-- clocks
A_CLK : in std_logic;
B_CLK : in std_logic;
-- inputs
A_EN : in std_logic;
B_EN : in std_logic;
A_WE : in std_logic;
B_WE : in std_logic;
A_ADDR : in std_logic_vector(15 downto 0);
B_ADDR : in std_logic_vector(15 downto 0);
A_DI : in std_logic_vector(39 downto 0);
B_DI : in std_logic_vector(39 downto 0);
A_BM : in std_logic_vector(39 downto 0);
B_BM : in std_logic_vector(39 downto 0);
A_CI : in std_logic;
B_CI : in std_logic;
-- outputs
A_DO : out std_logic_vector(39 downto 0);
B_DO : out std_logic_vector(39 downto 0);
A_ECC_1B_ERR : out std_logic;
B_ECC_1B_ERR : out std_logic;
A_ECC_2B_ERR : out std_logic;
B_ECC_2B_ERR : out std_logic
-- These ports are listed in the Primitives Doc, but p_r tool doesn't knows them:
-- FATAL ERROR: (51513): Component CC_BRAM_40K has no port name: A_CO
-- FATAL ERROR: (51513): Component CC_BRAM_40K has no port name: B_CO
-- A_CO : out std_logic;
-- B_CO : out std_logic
);
end component;
component CC_FIFO_40K
generic (
LOC : string := "UNPLACED"; -- Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED


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